参数资料
型号: ICS9250YF-30LF-T
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 0.300 INCH, SSOP-56
文件页数: 6/15页
文件大小: 337K
代理商: ICS9250YF-30LF-T
14
ICS9250-30
0398A—07/03/02
General Layout Precautions:
1) Use a ground plane on the top
routing layer of the PCB in all areas
not used by traces.
2) Make all power traces and ground
traces as wide as the via pad for
lower inductance.
Component Values:
C1 : Crystal load values determined by user
C2 : 22F/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01F ceramic
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and
series terminating resistor. Not
shown in all places to improve
readability of diagram.
2 Optional crystal load capacitors
are recommended. They should be
included in the layout but not
inserted unless needed.
Connections to VDD:
Power Groups:
Analog
VDDREF = X1, X2 PLL1
Digital
VDDPCI, VDDSDR, VDDLCPU, VDDLAPIC
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