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| 型号： | ICS94241FLF-T |
| 英文描述： | Programmable TCH⑩ for Differential PIII⑩ Processor |
| 中文描述： | 可编程清桦⑩⑩微分PIII处理器 |
| 文件页数： | 4/16页 |
| 文件大小： | 153K |
| 代理商： | ICS94241FLF-T |
4
ICS94241
0453C—10/26/04
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol.
The number of bytes to
readback is defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set.
If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
2.
3.
4.
5.
6.
7.
Notes:
Brief I
2
C registers description for ICS94241
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Functionality &
Frequency Select
Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte
description
See individual
byte
description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
Vendor ID & Revision ID
Registers
7
Byte 7 bit (7:4) is ICS vendor id -
001. Other bits in this register
designate device revision ID of this
part.
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
See individual
byte
description
Byte Count
Read Back Register
8
08
H
Watchdog Timer
Count Register
9
10
H
Watchdog Control
Registers
10 Bit [6:0]
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
VCO Control Selection
Bit
10 Bit [7]
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
0
VCO Frequency Control
Registers
11-12
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
description
Group Skews Control
Registers
15-16
Increment or decrement the group
skew amount as compared to the
initial skew.
Output Rise/Fall Time
Select Registers
17-20
These registers will control the
output rise and fall time.
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