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参数资料
| 型号： | ICS94241FLF-T |
| 英文描述： | Programmable TCH⑩ for Differential PIII⑩ Processor |
| 中文描述： | 可编程清桦⑩⑩微分PIII处理器 |
| 文件页数： | 6/16页 |
| 文件大小： | 153K |
| 代理商： | ICS94241FLF-T |
6
ICS94241
0453C—10/26/04
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
0
4
-
3
4
4
4
I
P
D
W
X
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
#
S
2
E
S
F
)
e
)
e
)
e
0
M
)
e
K
L
K
L
D
d
t
t
t
t
t
t
t
t
e
h
c
L
v
R
(
v
R
(
v
R
(
R
D
S
v
R
(
U
P
C
U
P
C
A
0
_
C
C
S
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
6
3
1
2
1
1
1
0
1
9
7
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
D
)
e
0
K
6
K
5
K
4
K
3
K
2
K
1
K
t
t
t
t
t
t
t
t
v
R
C
I
C
P
I
C
P
I
C
P
I
C
P
I
C
P
I
C
P
I
C
P
(
L
L
L
L
L
L
L
C
C
C
C
C
C
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
1
1
1
1
X
X
X
1
P
N
O
I
T
P
I
R
C
S
E
D
)
e
)
e
)
e
)
e
F
d
F
d
F
d
)
e
t
t
t
t
t
t
t
t
v
R
v
R
v
R
v
R
c
L
c
L
c
L
v
R
(
(
(
(
(
#
#
#
1
4
3
S
S
S
e
e
e
h
h
h
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
6
4
7
4
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
D
)
e
)
e
)
e
)
e
)
e
)
e
t
t
t
t
t
t
t
t
v
R
v
R
v
R
v
R
v
R
v
R
F
E
R
F
E
R
(
(
(
(
(
(
1
0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
0
1
X
X
X
X
X
X
P
N
O
I
T
P
I
R
C
N
N
N
N
N
N
N
N
S
(
(
(
(
(
(
(
(
E
d
d
d
d
d
d
d
d
D
e
e
e
e
e
e
e
e
7
6
5
4
3
2
1
0
)
)
)
)
)
)
)
)
v
R
v
R
v
R
v
R
v
R
v
R
v
R
v
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: This is an unused register writing to this register
will not affect device performance or functinality.
T
7
6
5
4
3
I
B
B
B
B
B
B
#
N
-
-
6
2
5
2
-
,
1
,
2
,
2
,
3
,
3
,
3
I
P
D
W
1
X
1
1
1
P
N
O
I
T
P
I
R
C
S
E
)
e
F
d
z
z
H
e
D
t
t
t
t
t
v
R
c
L
M
8
4
M
4
2
v
R
(
(
#
0
S
e
h
H
)
2
t
B
,
1
1
2
,
2
2
3
,
3
8
3
1
)
1
M
A
R
D
S
1
t
B
1
)
M
A
R
D
S
0
t
B
1
)
M
A
R
D
S
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