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参数资料
| 型号： | ICS950104YFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 166 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 1/19页 |
| 文件大小： | 222K |
| 代理商： | ICS950104YFT |
Integrated
Circuit
Systems, Inc.
ICS950104
Third party brands and names are the property of their respective owners.
Block Diagram
950104 Rev - 09/11/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
SIS630ST style chipset
Output Features:
1 - CPU clocks @ 2.5V
1 - Pair of differential CPU clocks @ 3.3V
9 - SDRAM @ 3.3V
7 - PCI @3.3V
1 - 48MHz, @3.3V
1 - 24/48MHz @ 3.3V
3 - REF @3.3V, (selectable strength) through I
2C
Features:
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable CPU, SDRAM, and PCI skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
Skew Specifications:
CPU - CPU: <250ps
PCI - PCI: <500ps
SDRAM - SDRAM: <250ps
CPU - SDRAM:<350ps
CPU - PCI: <3ns
Programmable System Clock Chip for PIII Processor
Notes:
REF0 can be 1X or 2X strength controlled by I
2C.
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down of 120K to GND
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
PCICLK (5:0)
PCICLK_F
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
MODE
MULTSEL
Control
Logic
Config.
Reg.
/ 2
REF(2:0)
CPUCLK
SDRAM (9:0)
SDRAM
DIVDER
Stop
10
6
3
CPUCLKT0
CPUCLKC0
Stop
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
CPUCLKC0
CPUCLKT0
VDDCPU
GND
AVDD
X1
X2
**FS0/REF0
VDDREF
**FS1/REF1
REF2
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDDPCI
PCICLK3
PCICLK4
PCICLK5
AVDD48
**MULTSEL/24_48MHz
**FS3/48MHz
GND
IREF
GND
CPUCLK
VDDL
SDATA
SDRAM_STOP#
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VDD
GND
SDRAM4
SDRAM5
SDRAM6
SDRAM7
GND
VDD
PCI_STOP#
CPU_STOP#
PD#/Vtt_PWRGD
SCLK
GND
*
#*
ICS950104
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2
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4
5
6
7
8
9
10
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12
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14
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24
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