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参数资料
| 型号： | ICS950104YFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 166 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 15/19页 |
| 文件大小： | 222K |
| 代理商： | ICS950104YFT |
5
ICS950104
Advance Information
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2C registers description for ICS950104
Programmable System Frequency Generator
Register N ame
Byte
Description
PWD Default
Functionality & Frequency
Select Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte w ill be
read back. Do not write 00H to this byte.
08H
Watchdog Timer
Count Register
9
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
10H
Watchdog Control Registers 10 Bit [6:0]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
10 Bit [7]
This bit select w hether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers ratio
into the phase detector and thus control
the V CO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
Registers
15-16
Increment or decrement the group skew
amount as compared to the initial skew .
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
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