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参数资料
| 型号： | ICS950813YFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, MO-118, SSOP-56 |
| 文件页数： | 11/22页 |
| 文件大小： | 253K |
| 代理商： | ICS950813YFT |
19
ICS950813
Advance Information
0708—10/10/02
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the power supply until the time that stable clocks are output from the clock chip. If the I
2C Bit 6 of Byte 0 is programmed
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagram
CPU 0.7V Configuration test load board termination
TLA
TLB
MULTSEL Pin must be High
Rs=33 Ohms
5%
Rs=33 Ohms
5%
Rp=49.9 Ohms
1%
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
2pF
5%
2pF
5%
CPUCLKT test
point
CPUCLKC test
point
CLK408
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| ICS950813YGT | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950818 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
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| ICS950901YFLFT | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for P4 |
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