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参数资料
| 型号： | ICS950813YFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, MO-118, SSOP-56 |
| 文件页数： | 9/22页 |
| 文件大小： | 253K |
| 代理商： | ICS950813YFT |
17
ICS950813
Advance Information
0708—10/10/02
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch
low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next
rising edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
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The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I
2C Bit 6 of Byte 1 is programmed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive
current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven . When the I
2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU
and CPU# outputs will not be driven.
CPU_STOP#
CPUCLKT
CPUCLKC
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