参数资料
型号: ICS951402YGLF-T
英文描述: Programmable Timing Control Hub for P4 processor
中文描述: 可编程定时控制中心的P4处理器
文件页数: 11/23页
文件大小: 303K
代理商: ICS951402YGLF-T
11
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2
C Table
: Output Divider Control Register
Byte 15
Pin #
Name
Control
Function
SDRAM divider ratio
can be configured
via these 4 bits
individually.
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
SD Div3
SD Div2
SD Div1
SD Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
See Table 2: Divider
Ratio Combination
Table
CPU divider ratio can
be configured via
these 4 bits
individually.
See Table 2: Divider
Ratio Combination
Table
Table 2:
CPU, SDRAM, AGP and PCI66 Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
1
00
0000
2
0100
01
0001
3
0101
10
0010
5
0110
11
0011
7
0111
LSB
Address
Div
Address
Table 3:
PCI33 Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
1
00
0000
4
0100
01
0001
3
0101
10
0010
5
0110
11
0011
7
0111
LSB
Address
Div
Address
10
1000
1001
1010
1011
Address
11
1100
1101
1110
1111
Address
MSB
8
16
24
40
56
Div
2
4
6
10
14
Div
4
8
12
20
28
Div
D
10
1000
1001
1010
1011
Address
11
1100
1101
1110
1111
Address
MSB
8
32
24
40
56
Div
2
8
6
10
14
Div
4
16
12
20
28
Div
D
相关PDF资料
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