参数资料
型号: ICS951402YGLF-T
英文描述: Programmable Timing Control Hub for P4 processor
中文描述: 可编程定时控制中心的P4处理器
文件页数: 14/23页
文件大小: 303K
代理商: ICS951402YGLF-T
14
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2
C Table
: Slew Rate Control Register
Byte 21
Pin #
Name
Control
Function
24_48 Slew Rate
Control
AGP Slew Rate
Control
Reserved
Reserved
REF Slew
Rate Control
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
24_48Slw1
24_48Slw0
AGPSlw1
AGPSlw0
Reserved
Reserved
REFSlw1
REFSlw0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
I
2
C Table
: Slew Rate Control Register
Byte 22
Pin #
Name
Control
Function
SDRAM Slew Rate
Control
Reserved
Reserved
PCI_F Slew Rate
Control
PCI Slew Rate
Control
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
SDSlw1
SDSlw0
Reserved
Reserved
PCISlw1
PCISlw0
PCISlw1
PCISlw0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
I
2
C Table
: Output Control Register
Byte 23
Pin #
Name
Control
Function
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Reserved
48MHz_1
SDRAM
48MHz_0
24_48MHz
REF2
REF1
REF0
-
-
-
X
1
1
1
1
1
1
1
27
47
28
26
4
3
2
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
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