参数资料
型号: ICS951402YGLF-T
英文描述: Programmable Timing Control Hub for P4 processor
中文描述: 可编程定时控制中心的P4处理器
文件页数: 8/23页
文件大小: 303K
代理商: ICS951402YGLF-T
8
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2
C Table
: Output Control Register
Byte 6
Pin #
Name
Control
Function
CPU Stop Status
PD# Status
Free-run Control
Free-run Control
Free-run Control
Free-run Control
Output Control
Output Control
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
CPU_STOP#
PD#
PCI_F0
PCI_F1
CPUT/C_0
CPUT/C_1
CPUT/C_0
CPUT/C_1
RW
RW
RW
RW
RW
RW
RW
RW
1
1
0
0
1
1
1
1
See Table 1:
Truth Table on page 3
Free
Free
Free
Free
Disable
Disable
Not free
Not free
Not free
Not free
Enable
Enable
40,39
44,43
I
2
C Table
: Output Control Register
Byte 7
Pin #
Name
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
23
22
21
20
17
16
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
I
2
C Table
:
Byte Count Register
Byte 8
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
1
Writing to this
register will configure
how many bytes will
be read back, default
is 0F
= 15 bytes.
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