参数资料
型号: ICS951402YGLF-T
英文描述: Programmable Timing Control Hub for P4 processor
中文描述: 可编程定时控制中心的P4处理器
文件页数: 12/23页
文件大小: 303K
代理商: ICS951402YGLF-T
12
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2
C Table
: Output Divider Control Register
Byte 16
Pin #
Name
Control
Function
AGP divider ratio can
be configured via
these 4 bits
individually
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
AGP Div3
AGP Div2
AGP Div1
AGP Div0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
See Table 2: Divider
Ratio Combination
Table
-
-
-
-
-
-
-
-
I
2
C Table
: Output Divider Control Register
Byte 17
Pin #
Name
Control
Function
AGP Phase Invert
Reserved
SDRAM
Phase Invert
CPU Phase Invert
PCI divider ratio can
be configured via
these 4 bits
individually
Type
0
1
PWD
Bit 7
Bit 6
-
-
AGPINV
Reserved
RW
RW
Default
-
Inverse
-
X
X
Bit 5
-
SDINV
RW
Default
Inverse
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
CPUINV
PCIDiv3
PCIDiv3
PCIDiv3
PCIDiv3
RW
RW
RW
RW
RW
Default
Inverse
X
X
X
X
X
See Table 2 & 3:
Divider Ratio
Combination Table
I
2
C Table
: Group Skew Control Register
Byte 18
Pin #
Name
Control
Function
CPUT
Skew Control
SDRAM
Skew Control
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
CPUSkw3
CPUSkw2
SDSkw3
SDSkw2
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
1
1
1
1
See 2-bit Skew
Control at table 4
See 2-bit Skew
Control at table 4
-
-
-
-
-
-
-
-
相关PDF资料
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