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参数资料
| 型号： | ICS95V860YHLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA72 |
| 封装： | LEAD FREE, BGA-72 |
| 文件页数： | 4/10页 |
| 文件大小： | 84K |
| 代理商： | ICS95V860YHLF-T |
3
ICS95V860
0675D—01/07/04
Pin Descriptions
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ICS95V860 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to thirteen
differential clock output pairs (CLKT[0:12], CLKC[0:12]) and one differential clock output feedback pair (FB_OUT,
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC) the input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is applied, the receivers
are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD is grounded, the PLL
is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL (appproximately 20MHz), the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
General Description
(continued)
相关PDF资料 |
PDF描述 |
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| ICS95V860YH-T | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA72 |
| ICSSSTV16857CG | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| ICSSSTV16857CL-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| ICSSSTV16857YG-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| ICSSSTV16857YLLF-T | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS95VLP857AGLF | 功能描述:IC CLOCK DRIVER 2.5V 48-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS95VLP857AGLFT | 功能描述:IC CLOCK DRIVER 2.5V 48-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS95VLP857AGLF-T | 制造商:INTEGRATED DEVICE TECHNOLOGY 功能描述: |
| ICS95VLP857AHLF | 功能描述:IC CLOCK DRIVER 2.5V 56-BGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS95VLP857AHLFT | 功能描述:IC CLOCK DRIVER 2.5V 56-BGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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