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参数资料
| 型号： | ICSSSTUAF32866CHLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封装： | LEAD FREE, MO-205CC, LFBGA-96 |
| 文件页数： | 12/31页 |
| 文件大小： | 562K |
| 代理商： | ICSSSTUAF32866CHLFT |
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ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
12
ICSSSTUAF32866C
7100/9
Terminal Functions
Terminal Name
Electrical
Characteristics
Ground Input
1.8V nominal
0.9V nominal
Input
Input
Differential Input
Differential Input
LVCMOS Input
LVCMOS Input
Description
GND
V
DD
V
REF
Z
OH
Z
OL
CLK
CLK
C0, C1
RESET
Ground
Power Supply Voltage
Input Reference Clock
Reserved for future use
Reserved for future use
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs
Asynchronous Reset Input. Resets registers and disables V
REF
data and clock differential-input receivers.
Chip Select Inputs. Disables outputs D1 - D24 output switching
when both inputs are HIGH.
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
The outputs of this register bit will not be suspended by the DCS
and CSR controls
The outputs of this register bit will not be suspended by the DCS
and CSR controls
Data Outputs that are suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Partial Parity Output. Indicates off parity of D1 - D25
Parity Input arrives one cycle after corresponding data input
Output Error bit, generated one cycle after the corresponding data
output
CSR, DCS
SSTL_18 Input
D1 - D25
SSTL_18 Input
DODT
SSTL_18 Input
DCKE
SSTL_18 Input
Q1 - Q25
QCS
1.8V CMOS
1.8V CMOS
QODT
1.8V CMOS
QCKE
1.8V CMOS
PPO
PAR_IN
QERR
1.8V CMOS
SSTL_18 Input
Open Drain Output
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| ICSSSTUAF32868A | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868AHLFT | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAH32865A | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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| ICTE-10 | GT 35C 35#12 SKT RECP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTUAF32868A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868AHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868B | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868BHLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32869A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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