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参数资料
| 型号： | ICSSSTUAF32868AHLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封装： | LEAD FREE, MO-246, LFBGA-176 |
| 文件页数： | 13/22页 |
| 文件大小： | 468K |
| 代理商： | ICSSSTUAF32868AHLFT |
ICSSSTUAF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
13
ICSSSTUAF32868A
7094/14
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 0°C to +70°C, V
DDQ
/V
DD
= 2.5V ± 0.2V.
Parameter
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
I
IL
All Inputs
Static Standby
Symbol
Test Conditions
Min.
1.2
Typ.
Max.
Units
V
V
μ
A
μ
A
I
OH
= -6mA, V
DDQ
= 1.7V
I
OL
= 6mA, V
DDQ
= 1.7V
V
I
= V
DD
or GND; V
DD
= 1.9V
I
O
= 0, V
DD
= 1.9V, RESET = GND
I
O
= 0, V
DD
= 1.9V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK = CLK = V
IH
(
AC
)
or V
IL
(
AC
)
I
O
= 0, V
DD
= 1.9V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK = V
IH
(
AC
), CLK =
V
IL
(
AC
)
I
O
= 0, V
DD
= 1.8V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK and CLK
switching 50% duty cycle
I
O
= 0, V
DD
= 1.8V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK and CLK
switching 50% duty cycle. One data
input switching at half clock frequency,
50% duty cycle.
V
I
= V
REF
± 250mV
V
ICR
= 0.9V, V
IPP
= 600mV
V
I
= V
DD
or GND
0.5
+5
200
10
-5
I
DD
Static Operating
mA
200
I
DDD
Dynamic Operating
(clock only)
260
μ
A/Clock
MHz
Dynamic Operating
(per each data input)
1:2 mode
75
μ
A/Clock
MHz/
Data
C
I
Data Inputs
CLK and CLK
RESET
2
3.5
4
pF
2.5
5
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| ICSSSTUAF32868B | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868BHLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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