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参数资料
| 型号： | ICSSSTUAF32868AHLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封装： | LEAD FREE, MO-246, LFBGA-176 |
| 文件页数： | 14/22页 |
| 文件大小： | 468K |
| 代理商： | ICSSSTUAF32868AHLFT |
ICSSSTUAF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
14
ICSSSTUAF32868A
7094/14
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol
f
CLOCK
t
W
t
ACT1,2
t
INACT1,3
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
DCS0 before CLK
↑
, CLK
↓
, DCS1 and CSGEN HIGH;
DCS1 before CLK
↑
, CLK
↓
, DCS0 and CSGEN HIGH;
DCS0 before CLK
↑
, CLK
↓
, DCS1 LOW and CSGEN
HIGH or LOW; DCS1 before CLK
↑
, CLK
↓
, DCS0
LOW and CSGEN HIGH or LOW
DODTn, DCKEn, PAR_IN, and data before CLK
↑
,
CLK
↓
DCSn, DODT,n DCKEn, and data after CLK
↑
, CLK
↓
PAR_IN after CLK
↑
, CLK
↓
V
DD
= 1.8V ± 0.1V
Min.
Units
MHz
ns
ns
ns
ns
Max.
410
1
1
2
a minimum time of t
ACT
(max) after RESET is taken HIGH.
3
V
REF
data and clock inputs must be held at valid input voltage levels (not floating) for a minimum time
of t
INACT
(max) after RESET is taken LOW.
This parameter is not production tested.
V
REF
must be held at a valid input voltage level and data inputs must be held at valid voltage levels for
10
15
t
SU
Setup
Time
0.7
0.5
ns
0.5
ns
t
H
Hold
Time
0.5
0.5
ns
ns
Symbol
f
MAX
t
PDM
t
PDMSS
t
LH
t
HL
t
PLH
t
PHL
Parameter
Max Input Clock Frequency
Propagation Delay, single bit switching, CLK
↑
to CLK
↓
to Qn
Propagation Delay, simultaneous switching, CLK
↑
to CLK
↓
to Qn
LOW to HIGH Propagation Delay, CLK
↑
to CLK
↓
to QERR
HIGH to LOW Propagation Delay, CLK
↑
to CLK
↓
to QERR
HIGH to LOW Propagation Delay, RESET
↓
to Qn
↓
LOW to HIGH Propagation Delay, RESET
↓
to QERR
↑
V
DD
= 1.8V ± 0.1V
Min.
410
1.3
Units
MHz
ns
ns
ns
ns
ns
ns
Max.
1.9
2
3
2.4
3
3
1.2
1
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相关代理商/技术参数 |
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| ICSSSTUAF32868B | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868BHLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32869A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32869AHLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAH32865A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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