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参数资料
| 型号： | IDT5T2010 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK |
| 中文描述： | 2.5V的零延迟PLL时钟驱动器TERACLOCK |
| 文件页数： | 16/23页 |
| 文件大小： | 157K |
| 代理商： | IDT5T2010 |
16
INDUSTRIAL TEMPERATURE RANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
AC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE
Symbol
Parameter
F
NOM
VCO Frequency Range
t
RPW
Reference Clock Pulse Width HIGH or LOW
t
FPW
Feedback Input Pulse Width HIGH or LOW
t
SK
(
B
)
Output Matched Pair Skew
(1,2,4)
t
SK
(
O
)
Output Skew (Rise-Rise, Fall-Fall, Nomnal)
(1,3)
t
SK
1
(
ω
)
Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nomnal-Divided, Divided-Divided)
(1,3,4)
t
SK
2
(
ω
)
Multiple Frequency Skew (Rise-Fall, Nomnal-Divided, Divided-Divided)
(1,3,4)
t
SK
1
(
INV
)
Inverting Skew (Nomnal-Inverted)
(1,3)
t
SK
2
(
INV
)
Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)
(1,3,4)
t
SK
(
PR
)
Process Skew
(1,3.5)
t(
φ
)
REF Input to FB Static Phase Offset
(6)
t
ODCV
Output Duty Cycle Variation from50%
(7)
Min.
see VCO Frequency Range Select Table
1
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-100
—
-375
—
-275
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
V
DDQ
/2 - 150
V
DDQ
/2
Typ.
Max
Unit
—
—
50
100
100
400
400
400
300
100
375
275
1.2
1
1.2
1
1
1
100
1
1
75
75
125
100
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
t
ORISE
Output Rise Time
(8)
ns
t
OFALL
Output Fall Time
(8)
ns
t
L
Power-up PLL Lock Time
(9)
PLL Lock Time After Input Frequency Change
(9)
PLL Lock Time After Change in REF_SEL
(9,11)
PLL Lock Time After Change in REF_SEL (REF
1
and REF
0
are different frequency)
(9)
PLL Lock Time After Asserting
PD
Pin
(9)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(10)
Period Jitter (peak-to-peak)
(10)
Half Period Jitter (peak-to-peak, QFB/
QFB
only)
(10, 12)
Duty Cycle Jitter (peak-to-peak)
(10)
HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level
QFB/
QFB
only
(12)
ms
ms
μ
s
ms
ms
ps
ps
ps
ps
mV
t
L
(
ω
)
t
L
(
REFSEL
1
)
t
L
(
REFSEL
2
)
t
L
(
PD
)
t
JIT
(
CC
)
t
JIT
(
PER
)
t
JIT
(
HP
)
t
JIT
(
DUTY
)
V
OX
V
DDQ
/2 + 150
NOTES:
1.
2.
3.
4.
5.
6.
Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
t
SK
(
B
) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.
The measurement is made at V
DDQ
/2.
There are three classes of outputs: nomnal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
t
SK
(
PR
) is the output to corresponding output skew between any two devices operating under the same conditions (V
DD
and V
DDQ
, ambient temperature, air flow, etc.).
t(
φ
) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken fromV
THI
on REF to V
THI
on
FB. For TxS/RxS = LOW, the measurement is taken fromthe crosspoint of REF/
REF
to the crosspoint of FB/
FB
. All outputs are set to zero delay, FB input divider set to divide-
by-one, and FS = HIGH.
t
ODCV
is measured with all outputs selected for zero delay.
Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
t
L
, t
L
(
ω
), t
L
(
REFSEL
1
), t
L
(
REFSEL
2
), and t
L
(
PD
) are the times that are required before the synchronization is achieved. These specifications are valid only after V
DD
/V
DDQ
is stable and
within the normal operating limts. These parameters are measured fromthe application of a new signal at REF or FB, or after
PD
is (re)asserted until t(
φ
) is within specified
limts.
10. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and FS = HIGH.
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.
12. For HSTL/eHSTL outputs only.
7.
8.
9.
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