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参数资料
| 型号： | IDT5T2010 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK |
| 中文描述： | 2.5V的零延迟PLL时钟驱动器TERACLOCK |
| 文件页数： | 4/23页 |
| 文件大小： | 157K |
| 代理商： | IDT5T2010 |
4
INDUSTRIAL TEMPERATURE RANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
NOTE:
1. Capacitance applies to all inputs except RxS, TxS, nF
[2:1]
, FBF
[2:1]
, and DS
[1:0]
.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
Description
C
IN
Input Capacitance
C
OUT
Output Capacitance
Min.
2.5
—
Typ.
3
6.3
Max.
3.5
7
Unit
pF
pF
Symbol
V
DDQ
, V
DD
V
I
V
O
V
REF
T
J
T
STG
Description
Max
Unit
V
V
V
V
°C
°C
Power Supply Voltage
(2)
Input Voltage
Output Voltage
Reference Voltage
(3)
Junction Temperature
Storage Temperature
–0.5 to +3.6
–0.5 to +3.6
–0.5 to V
DDQ
+0.5
–0.5 to +3.6
150
–65 to +165
ABSOLUTE MAX IMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
2. V
DDQ
and V
DD
internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
Symbol
T
A
V
DD
(1)
Description
Ambient Operating Temperature
Internal Power Supply Voltage
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
2.5V LVTTL Output Power Supply Voltage
Termnation Voltage
Min.
–40
2.3
1.4
1.65
Typ.
+25
2.5
1.5
1.8
V
DD
V
DDQ
/ 2
Max.
+85
2.7
1.6
1.95
Unit
°C
V
V
V
V
V
V
DDQ
(1)
V
T
RECOMMENDED OPERATING RANGE
NOTE:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
PIN DESCRIPTION
Symbol
I/O
REF
[1:0]
I
REF
[1:0]
/
I
V
REF
[1:0]
Type
Description
Clock input. REF
[1:0]
is the "true" side of the differential clock input. If operating in single-ended mode, REF
[1:0]
is the clock input.
Complementary clock input.
REF
[1:0]
/V
REF
[1:0]
is the "complementary" side of REF
[1:0]
if the input is in differential mode. If operating
in single-ended mode,
REF
[1:0]
/V
REF
[1:0]
is left floating. For single-ended operation in differential mode,
REF
[1:0]
/V
REF
[1:0]
should be set
to the desired toggle voltage for REF
[1:0]
:
2.5V LVTTL
V
REF
= 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
V
REF
= 900mV
HSTL
V
REF
= 750mV
LVEPECL
V
REF
= 1082mV
Clock input. FB is the "true" side of the differential feedback clock input. If operating in single-ended mode, FB is the feedback clock input.
Complementary feedback clock input.
FB
/V
REF
2
is the "complementary" side of FB if the input is in differential mode. If operating in single-
ended mode,
FB
/V
REF
2
is left floating. For single-ended operation in differential mode,
FB
/V
REF
2
should be set to the desired toggle voltage
for FB:
2.5V LVTTL
V
REF
= 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
V
REF
= 900mV
HSTL
V
REF
= 750mV
LVEPECL
V
REF
= 1082mV
Adjustable
(1)
Adjustable
(1)
FB
I
I
Adjustable
(1)
Adjustable
(1)
FB
/V
REF
2
NOTE:
1. All power supplies should operate in tandem If V
DD
or V
DDQ
is at maximum then V
DDQ
or V
DD
(respectively) should be at maximum and vice-versa.
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