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参数资料
| 型号： | IDT5T9010BBGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封装： | LEAD FREE, PLASTIC, BGA-144 |
| 文件页数： | 17/23页 |
| 文件大小： | 168K |
| 代理商： | IDT5T9010BBGI |
3
INDUSTRIALTEMPERATURERANGE
IDT5T9010
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TERACLOCK
NOTE:
1. Capacitance applies to all inputs except RxS, TxS, nF[2:0], FBF[2:0], and DS[1:0].
CAPACITANCE(TA=+25°C,f=1MHz,V
IN
= 0V)
Parameter
Description
Min.
Typ.
Max.
Unit
CIN
InputCapacitance
2.5
3
3.5
pF
COUT
OutputCapacitance
—
6.3
7
pF
Symbol
Description
Max
Unit
VDDQ, VDD
Power Supply Voltage(2)
–0.5 to +3.6
V
VI
Input Voltage
–0.5 to +3.6
V
VO
Output Voltage
–0.5 to VDDQ +0.5
V
VREF
Reference Voltage(3)
–0.5 to +3.6
V
TJ
Junction Temperature
150
° C
TSTG
Storage Temperature
–65 to +165
° C
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
Symbol
Description
Min.
Typ.
Max.
Unit
TA
AmbientOperatingTemperature
–40
+25
+85
° C
VDD(1)
Internal Power Supply Voltage
2.3
2.5
2.7
V
HSTL Output Power Supply Voltage
1.4
1.5
1.6
V
VDDQ(1)
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
1.65
1.8
1.95
V
2.5V LVTTL Output Power Supply Voltage
VDD
V
VT
TerminationVoltage
VDDQ / 2
V
RECOMMENDED OPERATING RANGE
NOTE:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
PIN DESCRIPTION
Symbol
I/O
Type
Description
REF[1:0]
I
Adjustable(1)
Clock input. REF[1:0] is the "true" side of the differential clock input. If operating in single-ended mode, REF[1:0] is the clock input.
REF[1:0]/
I
Adjustable(1)
Complementary clock input.
REF[1:0]/VREF[1:0]is the "complementary" side of REF[1:0] if the input is in differential mode. If operating
VREF[1:0]
in single-ended mode,
REF[1:0]/VREF[1:0]isleftfloating. Forsingle-endedoperationindifferentialmode,REF[1:0]/VREF[1:0]shouldbeset
to the desired toggle voltage for REF[1:0]:
2.5V LVTTL
VREF = 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
VREF = 900mV
HSTL
VREF = 750mV
LVEPECL
VREF = 1082mV
FB
I
Adjustable(1)
Clockinput. FBisthe"true"sideofthedifferentialfeedbackclockinput. Ifoperatinginsingle-endedmode,FBisthefeedbackclockinput.
FB/VREF2
I
Adjustable(1)
Complementaryfeedbackclockinput.
FB/VREF2isthe"complementary"sideofFBiftheinputisindifferentialmode. Ifoperatinginsingle-
endedmode,
FB/VREF2isleftfloating. Forsingle-endedoperationindifferentialmode, FB/VREF2shouldbesettothedesiredtogglevoltage
for FB:
2.5V LVTTL
VREF = 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
VREF = 900mV
HSTL
VREF = 750mV
LVEPECL
VREF = 1082mV
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
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