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参数资料
| 型号： | IDT5T9010BBGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封装： | LEAD FREE, PLASTIC, BGA-144 |
| 文件页数： | 3/23页 |
| 文件大小： | 168K |
| 代理商： | IDT5T9010BBGI |
11
INDUSTRIALTEMPERATURERANGE
IDT5T9010
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR
LVEPECL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max
Unit
Input Characteristics
IIH
Input HIGH Current
VDD = 2.7V
VI = VDDQ/GND
—
±5
μA
IIL
Input LOW Current
VDD = 2.7V
VI = GND/VDDQ
——
±5
VIK
Clamp Diode Voltage
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
V
VIN
DC Input Voltage
- 0.3
—
3.6
V
VCM
DC Common Mode Input Voltage(3,5)
915
1082
1248
mV
VREF
Single-EndedReferenceVoltage(4,5)
—
1082
—
mV
VIH
DC Input HIGH
1275
—
1620
mV
VIL
DC Input LOW
555
—
875
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode,
REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL
Symbol
Parameter
Value
Units
VDIF
Input Signal Swing(1)
732
mV
VX
Differential Input Signal Crossing Point(2)
1082
mV
VTHI
Input Timing Measurement Reference Level(3)
Crossing Point
V
tR, tF
Input Signal Edge Rate(4)
1
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
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相关代理商/技术参数 |
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| IDT5T9010BBGI8 | 功能描述:IC CLK DVR PLL PROGR 144-BGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:TeraClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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