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参数资料
| 型号： | IDT5T9110BBI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封装： | PLASTIC, BGA-144 |
| 文件页数： | 1/23页 |
| 文件大小： | 171K |
| 代理商： | IDT5T9110BBI8 |
1
INDUSTRIALTEMPERATURERANGE
IDT5T9110
2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
REF0
REF0/
VREF0
FB
FB/
VREF2
RxS
REF1
REF1/
VREF1
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
PLL
5
Q
5
Q
QFB
PD
FS
LOCK
PE
PLL_EN
0
1
/N
DS1:0
3
REF_SEL
0
1
Skew
Select
1F2:0
Skew
Select
2F2:0
Skew
Select
3F2:0
Skew
Select
4F2:0
Skew
Select
5F2:0
TxS
Skew
Select
FBF2:0
OMODE
PLL
1sOE
2sOE
3sOE
4sOE
5sOE
3
NOVEMBER 2004
2004
Integrated Device Technology, Inc.
DSC 5975/23
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
2.5 VDD
6 pairs of programmable skew outputs
Low skew: 100ps all outputs
Selectable positive or negative edge synchronization
Tolerant to spread spectrum input clock
Synchronous output enable
Selectable reference input
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
1.8V / 2.5V LVTTL: up to 250MHz
HSTL / eHSTL: up to 250MHz
Hot insertable and over-voltage tolerant inputs
3-level inputs for skew control
3-level inputs for selectable interface
3-level inputs for divide selection multiply/divide ratios of (1-6, 8,
10, 12) / (2, 4)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
Selectable differential or single-ended inputs and six differential
outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle
Power-down mode
Lock indicator
Available in BGA package
FUNCTIONAL BLOCK DIAGRAM
IDT5T9110
2.5V PROGRAMMABLE SKEW
PLL DIFFERENTIAL CLOCK
DRIVER TERACLOCK
DESCRIPTION:
The IDT5T9110 is a 2.5V PLL differential clock driver intended for high
performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5T9110 has six differential programmable skew
outputs in six banks, including a dedicated differential feedback. Skew is
controlled by 3-level input signals that may be hard-wired to appropriate
high-mid-low levels. The redundant input capability allows for a smooth
change over to a secondary clock source when the primary clock source
is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T9110 features a user-selectable, single-ended or differential
input to six differential outputs. The differential clock driver also acts as a
translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or
single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL
outputs. Selectable interface is controlled by 3-level input signals that may be
hard-wired to appropriate high-mid-low levels. The differential outputs can be
synchronously enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
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