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参数资料
| 型号： | IDT7006L55G |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 68PGA |
| 标准包装： | 3 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K (16K x 8) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-BPGA |
| 供应商设备封装： | 68-PGA（29.46x29.46） |
| 包装： | 托盘 |
| 其它名称： | 7006L55G |
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6)
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
____
____
____
____
15
15
15
15
____
____
____
____
17
17
17
17
____
____
____
____
20
20
20
17
____
____
____
____
20
20
20
17
ns
ns
ns
ns
t APS
t BDD
t WH
Arbitration Priority Set-up Time
BUSY Disable to Valid Data (3)
Write Hold After BUSY (5)
(2)
5
____
12
____
18
____
5
____
13
____
18
____
5
____
15
____
30
____
5
____
17
____
30
____
ns
ns
ns
BUSY TIMING (M/ S =V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
12
____
____
0
13
____
____
0
15
____
____
0
17
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
30
____
30
____
45
____
50
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
25
____
35
____
35
ns
2739 tbl 15a
7006X35 Com'l
& Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
t APS
t BDD
t WH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time (2)
BUSY Disable to Valid Data (3)
Write Hold After BUSY (5)
____
____
____
____
5
____
25
20
20
20
20
____
35
____
____
____
____
____
5
____
25
45
40
40
35
____
40
____
____
____
____
____
5
____
25
45
40
40
35
____
45
____
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING (M/ S =V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
25
____
____
0
25
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
60
____
80
____
95
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
____
80
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY ".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. 'X' is part numbers indicates power rating (S or L).
.
12
2739 tbl 15b
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IdT7006L55GB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 55NS 68PGA |
| IDT7006L55J | 功能描述:IC SRAM 128KBIT 55NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7006L55J8 | 功能描述:IC SRAM 128KBIT 55NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7006L55JB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
| IDT7006L55L68 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
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