参数资料
型号: IDT7006L55G
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/20页
文件大小: 0K
描述: IC SRAM 128KBIT 55NS 68PGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K (16K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-BPGA
供应商设备封装: 68-PGA(29.46x29.46)
包装: 托盘
其它名称: 7006L55G
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (5)
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
15
____
17
____
20
____
25
____
ns
t EW
Chip Enable to End-of-Write
(3)
12
____
12
____
15
____
20
____
ns
t AW
t AS
t WP
t WR
t DW
Address Valid to End-of-Write
Address Set-up Time (3)
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
12
0
12
0
10
____
____
____
____
____
12
0
12
0
10
____
____
____
____
____
15
0
15
0
15
____
____
____
____
____
20
0
20
0
15
____
____
____
____
____
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15
ns
t DH
Data Hold Time
(4)
0
____
0
____
0
____
0
____
ns
Write Enable to Output in High-Z
t WZ
(1,2)
____
____
____
____
____
12
____
15
ns
t OW
t SWRD
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,4)
0
5
5
____
____
____
0
5
5
____
____
____
0
5
5
____
____
____
0
5
5
____
____
____
ns
ns
ns
2739 tbl 14a
7006X35
Com'l & Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
35
____
55
____
70
____
ns
t EW
Chip Enable to End-of-Write
(3)
30
____
45
____
50
____
ns
t AW
Address Valid to End-of-Write
30
____
45
____
50
____
ns
t AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t WP
t WR
t DW
t HZ
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time (1,2)
25
0
15
____
____
____
____
15
40
0
30
____
____
____
____
25
50
0
40
____
____
____
____
30
ns
ns
ns
ns
t DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
Write Enable to Output in High-Z
t WZ
(1,2)
____
15
____
25
____
30
ns
t OW
t SWRD
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,4)
0
5
5
____
____
____
0
5
5
____
____
____
0
5
5
____
____
____
ns
ns
ns
2739 tbl 14b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested but not tested.
3. To access RAM, CE = V IL , SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . Either condition must be valid for the entire t EW time.
4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage
and temperature, the actual t DH will always be smaller than the actual t OW .
5. 'X' in part numbers indicates power rating (S or L).
9
6.42
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