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| 型号： | IDT7006L55G |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 68PGA |
| 标准包装： | 3 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K (16K x 8) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-BPGA |
| 供应商设备封装： | 68-PGA（29.46x29.46） |
| 包装： | 托盘 |
| 其它名称： | 7006L55G |
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY Arbitration
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A OL -A 13L
A OR -A 13R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
NOTES:
2739 tbl 18
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY X outputs on the IDT7006 are
push pull, not open drain outputs. On slaves the BUSY X input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
D 0 - D 7 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 7 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2739 tbl 19
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7006.
2. There are eight semaphore flags written to via I/O 0 and read from all I/O's. These eight semaphores are addressed by A 0 - A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7006 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7006 has an automatic power down feature controlled
by CE . The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected ( CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
( INT L ) is asserted when the right port writes to memory location 3FFE
(HEX) where a write is defined as CE = R/ W = V IL per the Truth Table .
The left port clears the interrupt by reading address location 3FFE access
when CE R = OE R = V IL, R/ W is a "don't care". Likewise, the right port
interrupt flag ( INT R ) is asserted when the left port writes to memory location
3FFF (HEX) and to clear the interrupt flag ( INT R ), the right port must read
the memory location 3FFF. The message (8 bits) at 3FFE or 3FFF is user-
defined, since it is an addressable SRAM location. If the interrupt function
is not used, address locations 3FFE and 3FFF are not used as mail boxes,
but as part of the random access memory. Refer to Truth Table III for the
interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
16
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IdT7006L55GB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 55NS 68PGA |
| IDT7006L55J | 功能描述:IC SRAM 128KBIT 55NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7006L55J8 | 功能描述:IC SRAM 128KBIT 55NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7006L55JB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
| IDT7006L55L68 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
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