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| 型号： | IDT7014S12JG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/9页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 36KBIT 12NS 52PLCC |
| 标准包装： | 12 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 36K（4K x 9） |
| 速度： | 12ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19x19） |
| 包装： | 管件 |
| 其它名称： | 7014S12JG |
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Timing Waveform of Write Cycle (1,2,3,4,5)
ADDRESS
OE
t AW
Industrial and Commercial Temperature Ranges
R/ W
t AS
t WP (5)
t WR
DATA OUT
(3)
t WZ (4)
t DW
t OW
t DH
t HZ
(3)
(4)
DATA IN
NOTES:
2528 drw 10
1. R/ W must be HIGH during all address transitions.
2. t WR is measured from R/ W going HIGH to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured 0mV from the Low or High-impedance voltage with the Output Test Load (Figure 2).
5. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be
placed on the bus for the required t DW . If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified t WP .
Functional Description
Truth Table I – Read/Write Control
The IDT7014 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to
any location in memory. It lacks the chip enable feature of CMOS Dual
Left or Right Port (1)
R/ W OE D 0-8
Function
Ports, thus it operates in active mode as soon as power is applied. Each
port has its own Output Enable control ( OE ). In the read mode, the port’s
OE turns on the output drivers when set LOW. The user application should
L
H
X
L
DATA IN Data written into memory
DATA OUT Data in memory output on port
avoid simultaneous write operations to the same memory location. There
X
H
Z
High-impedance outputs
is no on-chip arbitration circuitry to resolve write priority and partial data
from both ports may be written. READ/WRITE conditions are illustrated
in Table 1.
8
2528 tbl 10
NOTE:
1. A OL - A 11L is not equal to A OR - A 11R.
'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = HIGH Impedance.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7014S12JI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 4K x 9DUAL-PORT STATIC RAM |
| IDT7014S12PF | 功能描述:IC SRAM 36KBIT 12NS 64TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7014S12PF8 | 功能描述:IC SRAM 36KBIT 12NS 64TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7014S12PFG | 功能描述:IC SRAM 36KBIT 12NS 64TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7014S12PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 36KBIT 12NS 64TQFP |
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