参数资料
型号: IDT7015L35G
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/20页
文件大小: 0K
描述: IC SRAM 72KBIT 35NS 68PGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 72K(8K x 9)
速度: 35ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-BPGA
供应商设备封装: 68-PGA(29.46x29.46)
包装: 托盘
其它名称: 7015L35G
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6)
7015X12
Com'l Only
7015X15
Com'l Only
7015X17
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S = V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
____
____
____
____
12
12
12
12
____
____
____
____
15
15
15
15
____
____
____
____
17
17
17
17
ns
ns
ns
ns
BUSY Disable to Valid Data
Write Hold After BUSY
t APS
t BDD
t WH
Arbitration Priority Set-up Time
(3)
(5)
(2)
5
____
11
____
15
____
5
____
13
____
18
____
5
____
13
____
18
____
ns
ns
ns
BUSY INPUT TIMING (M/ S = V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
11
____
____
0
13
____
____
0
13
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
25
____
30
____
40
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
20
____
25
____
35
ns
2954 tbl 14a
7015X20
Com'l, Ind
& Military
7015X25
Com'l &
Military
7015X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S = V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
____
____
____
____
20
20
20
17
____
____
____
____
20
20
20
17
____
____
____
____
20
20
20
20
ns
ns
ns
ns
Write Hold After BUSY
t APS
t BDD
t WH
Arbitration Priority Set-up Time
BUSY Disable to Valid Data (3)
(5)
(2)
5
____
15
____
30
____
5
____
17
____
30
____
5
____
25
____
35
____
ns
ns
ns
BUSY INPUT TIMING (M/ S = V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
15
____
____
0
17
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
45
____
50
____
60
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
30
____
35
____
45
ns
NOTES:
2954 tbl 14b
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/ S = V IH )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
6.42
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