- 您现在的位置：买卖IC网 > Datasheet目录328 > IDT7015L35G (IDT, Integrated Device Technology Inc)IC SRAM 72KBIT 35NS 68PGA Datasheet资料下载
参数资料
| 型号： | IDT7015L35G |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 72KBIT 35NS 68PGA |
| 标准包装： | 3 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 72K（8K x 9） |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-BPGA |
| 供应商设备封装： | 68-PGA（29.46x29.46） |
| 包装： | 托盘 |
| 其它名称： | 7015L35G |
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Truth Table IV — Address BUSY
Arbitration
Military, Industrial and Commercial Temperature Ranges
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A OL -A 12L
A OR -A 12R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
2954 tbl 17
NOTES:
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY X outputs on the IDT7015 are
push-pull, not open drain outputs. On slaves the BUSY X input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
D 0 - D 15 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 15 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2954 tbl 18
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015.
2. There are eight semaphore flags written to via I/O 0 and read from all I/O s (I/O 0 - I/O 8 ). These eight semaphores are addressed by A 0 - A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7015 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7015 has an automatic power down feature controlled
by CE . The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected ( CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
( INT L ) is asserted when the right port writes to memory location 1FFE
where a write is defined as the CE = R/ W = V IL per Truth Table III. The
left port clears the interrupt by an address location 1FFE access when CE R
= OE R =V IL , R/ W is a "don't care". Likewise, the right port interrupt flag
(INT R ) is asserted when the left port writes to memory location 1FFF and
to clear the interrupt flag ( INT R ), the right port must access memory location
1FFF. The message (9 bits) at 1FFE or 1FFF isuser-defined since it is
an addressable SRAM location. If the interrupt function is not used, address
locations 1FFE and 1FFF are not used as mail boxes but are still part
of the random access memory. Refer to Table III for the interrupt
operation.
16
6.42
相关PDF资料 |
PDF描述 |
|---|---|
| IDT7016L35G | IC SRAM 144KBIT 35NS 68PGA |
| IDT7019L20PFI | IC SRAM 1.125MBIT 20NS 100TQFP |
| IDT7024L55G | IC SRAM 64KBIT 55NS 84PGA |
| IDT7025L55G | IC SRAM 128KBIT 55NS 84PGA |
| IDT70261L20PFI | IC SRAM 256KBIT 20NS 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7015L35GB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015L35GI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015L35J | 功能描述:IC SRAM 72KBIT 35NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT7015L35J8 | 功能描述:IC SRAM 72KBIT 35NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7015L35JB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
发布紧急采购，3分钟左右您将得到回复。