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参数资料
| 型号： | IDT7016L35G |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 144KBIT 35NS 68PGA |
| 标准包装： | 3 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 144K（16K x 9） |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-BPGA |
| 供应商设备封装： | 68-PGA（29.46x29.46） |
| 包装： | 托盘 |
| 其它名称： | 7016L35G |
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6)
7016X12
Com'l Only
7016X15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S = V IH )
t BAA
t BDA
t BAC
t BDC
t APS
t BDD
t WH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disab le Time from Chip Enable High
Arbitration Priority Set-up Time (2)
BUSY Disable to Valid Data (3)
Write Hold After BUSY (5)
____
____
____
____
5
____
11
12
12
12
12
____
15
____
____
____
____
____
5
____
13
15
15
15
15
____
18
____
ns
ns
ns
ns
ns
ns
ns
BUSY INPUT TIMING (M/ S = V IL )
t WB
t WH
BUSY Input to Write (4)
Write Hold After BUSY (5)
0
11
____
____
0
13
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
25
____
30
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
20
____
25
ns
3190 tbl 14a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S = V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disab le Time from Chip Enable High
____
____
____
____
20
20
20
17
____
____
____
____
20
20
20
17
____
____
____
____
20
20
20
20
ns
ns
ns
ns
BUSY Disable to Valid Data
Write Hold After BUSY
t APS
t BDD
t WH
Arbitration Priority Set-up Time
(3)
(5)
(2)
5
____
15
____
30
____
5
____
17
____
30
____
5
____
25
____
35
____
ns
ns
ns
BUSY INPUT TIMING (M/ S = V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
15
____
____
0
17
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
45
____
50
____
60
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
30
____
35
____
45
ns
NOTES:
3190 tbl 14b
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/ S = V IH )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
6.42
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相关代理商/技术参数 |
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|---|---|
| IDT7016L35GB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
| IDT7016L35GG | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L35GGB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L35GGI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L35J | 功能描述:IC SRAM 144KBIT 35NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
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