参数资料
型号: IDT7038L15PFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/17页
文件大小: 0K
描述: IC SRAM 1024KBIT 15NS 120TQFP
标准包装: 12
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1.125M(64K x 18)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
IDT7038L
High-Speed 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
5V
5V
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
GND to 3.0V
3ns Max.
1.5V
DATA OUT
BUSY
893 ?
DATA OUT
893 ?
Output Reference Levels
1.5V
INT
347 ?
30pF
347 ?
5pF*
Output Load
Figures 1 and 2
4837 tbl 11
4837 drw 03
Figure 1. AC Output Test Load
4837 drw 04
Figure 2. Output Test Load
.
(for t LZ , t HZ , t WZ , t OW )
* Including scope and jig.
Waveform of Read Cycles (5)
t RC
ADDR
CE
(6)
(4)
t AA
(4)
t ACE
t AOE
(4)
OE
t ABE (4)
UB , LB
R/ W
DATA OUT
BUSY OUT
t LZ
(1)
VALID DATA
(4)
t HZ
t OH
(2)
Timing of Power-Up Power-Down
(6)
CE
t BDD
(3,4)
4837 drw 05
I CC
t PU
50%
t PD
50%
I SB
4837 drw 06 .
NOTES:
1. Timing depends on which signal is asserted last, OE , CE , LB or UB .
2. Timing depends on which signal is de-asserted first CE , OE , LB or UB .
3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA or t BDD .
5. SEM = V IH .
6. Refer to Chip Enable Truth Table.
6
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