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参数资料
| 型号： | IDT70V25L25PFGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 21/25页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 25NS 100TQFP |
| 标准包装： | 45 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 25ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 1254 (CN2011-ZH PDF) |
| 其它名称： | 70V25L25PFGI 800-1389 |
IDT70V35/34S/L (IDT70V25/24S/L)
Truth Table III — Interrupt Flag
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
(1)
Left Port
Industrial and Commercial Temperature Ranges
Right Port
A 12R -A 0R
R/ W L
CE L
OE L
A 12L -A 0L
(4)
INT L
R/ W R
CE R
OE R
(4)
INT R
Function
L
X
L
X
X
X
1FFF (4)
X
X
X
X
X
X
L
X
L
X
1FFF (4)
L (2)
H (3)
Set Right INT R Flag
Reset Right INT R Flag
L
X
X
X
X
(3)
L
L
X
1FFE
(4)
X
Set Left INT L Flag
H
X
L
L
1FFE
(4)
(2)
X
X
X
X
X
Reset Left INT L Flag
NOTES:
1. Assumes BUSY L = BUSY R = V IH .
2. If BUSY L = V IL , then no change.
3. If BUSY R = V IL , then no change.
4. A 12 is a NC for IDT70V34 and for IDT70V24, therefore Interrupt Addresses are FFF and FFE.
Truth Table IV — Address BUSY
Arbitration
5624 tbl 15
Inputs
Outputs
A 12L -A 0L
CE L
X
H
X
L
CE R
X
X
H
L
(4)
A 12R -A 0R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
Note (2)
BUSY R (1)
H
H
H
Note (2)
Function
Normal
Normal
Normal
Write Inhibit (3)
NOTES:
5624 tbl 16
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V35/34 (IDT70V25/24) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. V IH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
4. A 12 is a NC for IDT70V34 and for IDT70V24. Address comparison will be for A 0 - A 11 .
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
D 0 - D 17 Left (2)
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 17 Right (2)
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5624 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34 (IDT70V25/24).
2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O 0 -I/O 17 for IDT70V35/34) and (I/O 0 -I/O 15 for IDT70V25/24). These eight semaphores
are addressed by A 0 -A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.
21
6.42
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