参数资料
型号: IDT70V3599S166BFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 15/23页
文件大小: 0K
描述: IC SRAM 4MBIT 166MHZ 208FPBGA
标准包装: 7
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 4.5M(128K x 36)
速度: 166MHz
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 托盘
产品目录页面: 1254 (CN2011-ZH PDF)
其它名称: 70V3599S166BFG
800-1396
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
( OE = V IL ) (2) t CYC2
t CH2 t CL2
CLK
CE 0
CE 1
t SC
t SB
t HC
t HB
BE n
t SW t HW
R/ W
t SW t HW
(3)
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
DATA IN
t SA
t HA
t SD t HD
Dn + 2
DATA OUT
(1)
t CD2
Qn
t CKHZ
t CKLZ
t CD2
Qn + 3
READ
NOP
(4)
WRITE
READ
NOTES:
5617 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0 , BE n , and ADS = V IL ; CE 1 and REPEAT = V IH . "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) (2)
t CYC2
CLK
CE 0
t CH2
t CL2
CE 1
t SC
t SB
t HC
t HB
BE n
t SW t HW
R/ W
t SW t HW
(3)
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
t SA
t HA
t SD
t HD
DATA IN
(1)
t CD2
Dn + 2
Dn + 3
t CKLZ
t CD2
DATA OUT
Qn
(4)
Qn + 4
t OHZ
OE
NOTES:
READ
WRITE
READ
5617 drw 13
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0 , BE n , and ADS = V IL ; CE 1 and REPEAT = V IH .
3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
15
6.42
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