参数资料
型号: IDT70V7319S166DDI
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/21页
文件大小: 0K
描述: IC SRAM 4MBIT 166MHZ 144TQFP
产品变化通告: Product Discontinuation 20/Aug/2008
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 4.5M(256K x 18)
速度: 166MHz
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
封装/外壳: 144-LQFP 裸露焊盘
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
其它名称: 70V7319S166DDI
IDT70V7319S
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Port A Write to Pipelined Port B Read (1,2,4)
CLK "A"
R/ W "A"
t SW
t SA
t HW
t HA
BANK ADDRESS
AND ADDRESS "A"
An
t SD
t HD
DATA IN"A"
Dn
t CO (3)
CLK "B"
t CD2
R/ W "B"
t SW
t SA
t HW
t HA
BANK ADDRESS
AND ADDRESS "B"
DATA OUT"B"
An
Dn
t DC
NOTES:
5629 drw 10
1. CE 0 , BE n, and ADS = V IL ; CE 1 , CNTEN , and REPEAT = V IH .
2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to.
3. If t CO < minimum specified, then operations from both ports are INVALID. If t CO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle
(ie, time from write to valid read on opposite port will be t CO + t CYC2 + t CD2 ).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform with Port-to-Port Flow-Through Read (1,2,4)
CLK "A"
t SW t HW
R/ W "A"
t SA
t HA
BANK ADDRESS
AND ADDRESS "A"
An
t SD
t HD
DATA IN "A"
Dn
t CO (3)
CLK "B"
t CD1
R/ W "B"
BANK ADDRESS
AND ADDRESS "B"
t SW
t SA
An
t HW
t HA
DATA OUT "B"
t DC
Dn
t DC
5622 drw 11
NOTES:
1. CE 0 , BE n, and ADS = V IL ; CE 1 , CNTEN , and REPEAT = V IH .
2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to.
3. If t CO < minimum specified, then operations from both ports are INVALID. If t CO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle
(i.e., time from write to valid read on opposite port will be t CO + t CD1 ).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
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