参数资料
型号: IDT7132SA55C
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/16页
文件大小: 0K
描述: IC SRAM 16KBIT 55NS 48DIP
标准包装: 8
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 48-DIP(0.600",15.24mm)
供应商设备封装: 48-SIDE BRAZED
包装: 管件
其它名称: 7132SA55C
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (2,3,4)
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
t DW
t DH
t APS
DATA IN"A"
ADDR "B"
(1)
VALID
MATCH
t BAA
t BDA
t BDD
BUSY "B"
t WDD
DATA OUT"B"
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for Slave (IDT7142).
t DDD
VALID
2692 drw 11
2.
3.
CE L = CE R = V IL
OE = V IL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY (4)
t WP
R/ W "A"
t WB (3)
BUSY "B"
t WH (1)
R/ W "B"
(2)
,
2692 drw 12
NOTES:
1.
2.
t WH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
BUSY is asserted on port "B" blocking R/ W "B" , until BUSY "B" goes HIGH.
3. t WB applies only to the slave version (IDT7142).
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
12
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