参数资料
型号: IDT7132SA55C
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/16页
文件大小: 0K
描述: IC SRAM 16KBIT 55NS 48DIP
标准包装: 8
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 48-DIP(0.600",15.24mm)
供应商设备封装: 48-SIDE BRAZED
包装: 管件
其它名称: 7132SA55C
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing (1)
"A"
ADDR
and "B"
CE "B"
CE "A"
t APS (2)
t BAC
ADDRESSES MATCH
t BDC
BUSY "A"
2692 drw 13
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing (1)
t RC or t WC
t APS
ADDR "A"
ADDR "B"
(2)
ADDRESSES MATCH
t BAA
ADDRESSES DO NOT MATCH
t BDA
BUSY "B"
2692 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
Truth Tables
Table I. Non-Contention Read/Write Control (4)
Left or Right Port (1)
R/ W
X
X
L
H
X
CE
H
H
L
L
L
OE
X
X
X
L
H
D 0-7
Z
Z
DATA IN
DATA OUT
Z
Function
Port Disabled and in Power-Down Mode, I SB2 or I SB4
CE R = CE L = V IH, Power-Down Mode, I SB1 or I SB3
Data on Port Written into Memory (2)
Data in Memory Output on Port (3)
High Impedance Outputs
NOTES:
1. A 0L - A 10L ≠ A 0R - A 10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t WDD and t DDD timing.
4. 'H' = V IH , 'L' = V IL , 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
13
6.42
2692 tbl 12
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