参数资料
型号: IDT71V432S6PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/18页
文件大小: 0K
描述: IC SRAM 1MBIT 6NS 100TQFP
标准包装: 72
格式 - 存储器: RAM
存储器类型: SRAM - 同步
存储容量: 1M(32K x 32)
速度: 6ns
接口: 并联
电源电压: 3.135 V ~ 3.63 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 71V432S6PF
32K x 32 CacheRAM ?
3.3V Synchronous SRAM
Burst Counter
Single Cycle Deselect
IDT71V432
Features
processor interfaces. The pipelined burst architecture provides cost-
32K x 32 memory configuration
Supports high-performance system speed:
Commercial and Industrial:
— 5ns Clock-to-Data Access (100MHz)
— 6ns Clock-to-Data Access (83MHz)
— 7ns Clock-to-Data Access (66MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control ( GW ), byte
write enable ( BWE ), and byte writes ( BW x)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
effective 3-1-1-1 secondary cache performance for processors up to
100 MHz.
The IDT71V432 CacheRAM contains write, data, address, and
control registers. Internal logic allows the CacheRAM to generate a self-
timed write based upon a decision which can be left until the extreme end
of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V432 can provide four cycles of data for
a single address presented to the CacheRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected ( ADV =LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses will be defined by the internal burst counter
and the LBO input pin.
Description
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM
organized as 32K x 32 with full support of the Pentium? and PowerPC?
Pin Description Summary
The IDT71V432 CacheRAM utilizes IDT's high-performance, high-
volume 3.3V CMOS process, and is packaged in a JEDEC Standard
14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board
density in both desktop and notebook applications.
A 0 –A 14
CE
CS 0 , CS 1
OE
GW
BWE
BW 1, BW 2, BW 3, BW 4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O 0 –I/O 31
V DD
V SS
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Ground
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
DC
DC
3104 tbl 01
CacheRAM is a trademark of Integrated Device Technology.
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
?2005 Integrated Device Technology, Inc.
1
OCTOBER 2008
DSC-3104/06
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