参数资料
型号: IDT71V67602S133BQG
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/23页
文件大小: 0K
描述: IC SRAM 9MBIT 133MHZ 165FBGA
产品变化通告: Product Discontinuation 05/Nov/2008
标准包装: 136
格式 - 存储器: RAM
存储器类型: SRAM - 同步
存储容量: 9M(256K x 36)
速度: 133MHz
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 165-TBGA
供应商设备封装: 165-CABGA(13x15)
包装: 托盘
其它名称: 71V67602S133BQG
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Pin Definitions (1)
Commercial and Industrial Temperature Ranges
Symbol
A 0 -A 18
ADSC
ADSP
ADV
Pin Function
Address Inputs
Address Status
(Cache Controller)
Address Status
(Processor)
Burst Address
Advance
I/O
I
I
I
I
Active
N/A
LOW
LOW
LOW
Description
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE .
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE
BW 1 - BW 4
CE
CLK
Byte Write Enable
Individual Byte
Write Enables
Chip Enable
Clock
I
I
I
I
LOW
LOW
LOW
N/A
Synchronous byte write enable gates the byte write inputs BW 1 - BW 4 . If BWE is LOW at the
rising edge of CLK then BW x inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
Synchronous byte write enables. BW 1 controls I/O 0-7 , I/O P1 , BW 2 controls I/O 8-15 , I/O P2 , etc.
Any active byte write causes all outputs to be disabled.
Synchronous chip enable. CE is used with CS 0 and CS 1 to enable the IDT71V67602/7802.
CE also gates ADSP .
This is the clock input. All timing references for the device are made with respect to this
input.
CS 0
CS 1
GW
I/O 0 -I/O 31
Chip Select 0
Chip Select 1
Global Write
Enable
Data Input/Output
I
I
I
I/O
HIGH
LOW
LOW
N/A
Synchrono us active HIGH chip select. CS 0 is used with CE and CS 1 to enable the chip.
Synchronous active LOW chip select. CS 1 is used with CE and CS 0 to enable the chip.
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
I/O P1 -I/O P4
registered and triggered by the rising edge of CLK.
LBO
OE
V DD
V DDQ
V SS
NC
ZZ
Linear Burst Order
Output Enable
Power Supply
Power Supply
Ground
No Connect
Sleep Mode
I
I
N/A
N/A
N/A
N/A
I
LOW
LOW
N/A
N/A
N/A
N/A
HIGH
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
3.3V core power supply.
2.5V I/O Supply.
Ground.
NC pins are not electrically connected to the device.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67602/7802 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
5311 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
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IDT71V67602S133BQG8 功能描述:IC SRAM 9MBIT 133MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M(64M x 8) 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP(0.724",18.40mm 宽) 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040
IDT71V67602S133BQGI 功能描述:IC SRAM 9MBIT 133MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M(64M x 8) 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP(0.724",18.40mm 宽) 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040
IDT71V67602S133BQGI8 功能描述:IC SRAM 9MBIT 133MHZ 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M(64M x 8) 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP(0.724",18.40mm 宽) 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040
IDT71V67602S133BQI 功能描述:IC SRAM 9MBIT 133MHZ 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M(64M x 8) 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP(0.724",18.40mm 宽) 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040
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