参数资料
型号: IDT72261LA20TFI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 18/27页
文件大小: 0K
描述: IC FIFO 8192X18 LP 20NS 64QFP
标准包装: 1,250
系列: 7200
功能: 同步
存储容量: 144K(8K x 18)
数据速率: 50MHz
访问时间: 20ns
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 带卷 (TR)
其它名称: 72261LA20TFI8
25
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72261LA/72271LA SuperSync FIFO
16,384 x 9 and 32,768 x 9
Figure 20. Block Diagram of 32,768 x 9 and 65,536 x 9 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72261LA can easily be adapted to applications requiring depths
greater than 16,384 and 32,768 for the IDT72271LA with a 9-bit bus width.
InFWFTmode,theFIFOscanbeconnectedinseries(thedataoutputsofone
FIFOconnectedtothedatainputsofthenext)withnoexternallogicnecessary.
Theresultingconfigurationprovidesatotaldepthequivalenttothesumofthe
depthsassociatedwitheachsingleFIFO. Figure22showsadepthexpansion
using two IDT72261LA/72271LA devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOsinthedepthexpansionconfiguration. Thefirstwordwrittentoanempty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the
datawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoesLOW,
enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW3
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
IDT
72261LA
72271LA
TRANSFER CLOCK
4671 drw 23
n
FWFT/SI
IDT
72261LA
72271LA
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequentwordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
moves into the first FIFO of the chain. Each time a free location is created in
one FIFO of the chain, that FIFO's IRlinegoesLOW,enablingthepreceding
FIFO to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFO in the chain to go LOW after a word has been read from the last FIFO
is the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly
as possible, to the end of the chain and free locations to the beginning of
the chain.
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