参数资料
型号: IDT72261LA20TFI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/27页
文件大小: 0K
描述: IC FIFO 8192X18 LP 20NS 64QFP
标准包装: 1,250
系列: 7200
功能: 同步
存储容量: 144K(8K x 18)
数据速率: 50MHz
访问时间: 20ns
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 带卷 (TR)
其它名称: 72261LA20TFI8
14
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72261LA/72271LA SuperSync FIFO
16,384 x 9 and 32,768 x 9
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition
that shifts the last word from the FIFO memory to the outputs. OR goes
HIGH only with a true read (RCLK with REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing (FWFT
Mode), for the relevant timing information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The PAF will go LOW after (16,384-m) writes for the
IDT72261LA and (32,768-m) writes for the IDT72271LA. The offset “m” is
the full offset value. The default setting for this value is stated in the footnote
of Table 1.
In FWFT mode, the PAF will go LOW after (16,385-m) writes for the
IDT72261LA and (32,769-m) writes for the IDT72271LA, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go
LOW when there are n words or less in the FIFO. The offset “n” is the empty
offset value. The default setting for this value is stated in the footnote of
Table 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in the footnote of Table
2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills the
FIFO beyond half-full sets HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or equal
to half of the total depth of the device; the rising RCLK edge that accom-
plishes this condition sets HF HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 16,384
for the IDT72261LA and 32,768 for the IDT72271LA.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385 for the
IDT72261LA and 32,769 for the IDT72271LA.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Q8)
(Q0 - Q8) are data outputs for 9-bit wide data.
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