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参数资料
| 型号： | IDT723646L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/35页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 2048X36 128QFP |
| 标准包装： | 72 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 72K（2K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723646L12PF |
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10
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2)
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT723626/723636/723646 undergoes a complete reset by
takingitsassociatedMasterReset(
MRS1)inputLOWforatleastfourPortAClock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a complete reset by taking its associated Master Reset
(
MRS2)inputLOWforatleastfourPortAClock(CLKA)andfourPortCClock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch asyn-
chronouslytotheclocks.AMasterResetinitializestheassociatedreadandwrite
pointers to the first location of the memory and forces the Full/Input Ready flag
(
FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (
AEA,AEB)LOW,andtheAlmost-Fullflag
(
AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(
MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraMasterReset,the
FIFO’s Full/Input Ready flag is set HIGH after two Write clock cycles. Then the
FIFO is ready to be written to.
A LOW-to-HIGH transition on a FlFO1 Master Reset (
MRS1,MRS2)input
latchesthevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhich
bytesaretransferredthroughportsBandC.ItalsolatchesthevaluesoftheFlag
Select (FS0, FS1) and Serial Programming Mode (
SPM) inputs for choosing
theAlmost-FullandAlmost-Emptyoffsetprogrammingmode.
ALOW-to-HIGHtransitionontheFIFO2MasterReset(
MRS2)clearstheflag
offsetregistersofFIFO2(X2,Y2).ALOW-to-HIGHtransitionontheFIFO2Master
Resetinput(
MRS2)latchesthevalueoftheBig-Endian(BE)inputforPortsBand
CandalsolatchesthevaluesoftheFlagSelect(FS0,FS1)andSerialProgramming
Mode(
SPM)inputsforchoosingtheAlmost-FullandAlmost-Emptyoffsetprogram-
mingmethod(fordetailsseeTable1,FlagProgramming,andAlmost-Emptyand
Almost-FullFlagOffsetProgrammingsection).TherelevantMasterResettiming
diagrams can be found in Figure 4 and 5.
NotethatMBCmustbeHIGHduringMasterReset(until
FFA/IRAandFFC/
IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master Reset.
PARTIAL RESET (
PRS1, PRS2)
The FIFO1 memory of these devices undergoes a limited reset by taking
its associated Partial Reset (
PRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memoryundergoesalimitedresetbytakingitsassociatedPartialReset(
PRS2)
input LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC)
LOW-to-HIGHtransitions.ThePartialResetinputscanswitchasynchronously
to the clocks. A Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (
FFA/IRA,FFC/IRC)LOW,theEmpty/Output
Ready flag (
EFA/ORA,EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB)
LOW, and the Almost-Full flag (
AFA, AFC) HIGH. A Partial Reset also forces
the Mailbox Flag (
MBF1, MBF2)oftheparallelmailboxregisterHIGH.Aftera
PartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteclock
cycles.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Reset is initiated, those settings will remain unchanged upon completion of the
resetoperation.APartialResetmaybeusefulinthecasewherereprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
ENDIAN SELECTION
This is a dual purpose pin. At the time of Master Reset, the BE select
function is active, permitting a choice of Big- or Little-Endian byte arrange-
ment for data written to Port C or read from Port B. This selection determines
the order by which bytes (or words) of data are transferred through those
ports.Forthefollowingillustrations,notethatbothportsBandCareconfigured
to have a byte (or a word) bus size.
AHIGHontheBE/
FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
go from LOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction from Port A to Port B, the most significant byte (word) of
the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.
A LOW on the BE/
FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figures 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.
TIMING MODE SELECTION
After Master Reset, the FWFT select function is available, permitting a
choice between two possible timing modes: IDT Standard mode or First
Word Fall Through (FWFT) mode. Once the Master Reset (
MRS1, MRS2)
input is HIGH, a HIGH on the BE/
FWFT input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKC (for FIFO2) will select IDT Standard
mode.ThismodeusestheEmptyFlagfunction(
EFA,EFB)toindicatewhether
or not there are any words present in the FIFO memory. It uses the Full Flag
function (
FFA,FFC)toindicatewhetherornottheFIFOmemoryhasanyfree
space for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using a formal read operation.
Once the Master Reset (
MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKC (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B17). It also uses the Input Ready function (IRA, IRC)
to indicate whether or not the FIFO memory has any free space for writing. In
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytothedata
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
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相关代理商/技术参数 |
参数描述 |
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| IDT723646L12PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L15PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L15PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723651L15PF | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723651L15PF8 | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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