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参数资料
| 型号： | IDT723646L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 23/35页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 2048X36 128QFP |
| 标准包装： | 72 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 72K（2K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723646L12PF |
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3
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (
MBF1 and MBF2) to signal when
new mail has been stored.
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial
Reset. Master Reset initializes the read and write pointers to the first location
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram-
ming,or oneofthreepossibledefaultflagoffsetsettings,8,16or64. EachFIFO
has its own, independent Master Reset pin,
MRS1 and MRS2.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
These devices have two modes of operation: In the IDT Standard
mode, the first word written to an empty FIFO is deposited into the memory
array. A read operation is required to access that word (along with all other
words residing in memory). In the First Word Fall Through mode (FWFT),
the first word written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/
FWFTpin
during Master Reset determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC).
The
EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty.
FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEAandAEB)and
aprogrammableAlmost-Fullflag(
AFAandAFC).AEAandAEBindicatewhen
aselectednumberofwordsremainintheFIFOmemory.
AFAandAFCindicate
when the FIFO contains more than a selected number of words.
FFA/IRA,FFC/IRC,AFAandAFCaretwo-stagesynchronizedtothePort
Clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA, and AEB are
two-stage synchronized to the Port Clock that reads data from its array.
Programmableoffsetsfor
AEA,AEB,AFA,AFCareloadedinparallelusingPort
A or in serial via the SD input. The Serial Programming Mode pin (
SPM)makes
thisselection.Threedefaultoffsetsettingsarealsoprovided.The
AEAandAEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFAandAFCthresholdcanbesetat8,16or64locationsfromthefullboundary.
AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset.
Two or more FIFOs may be used in parallel to create wider data paths.
Such a width expansion requires no additional, external components. Further-
more, two IDT723626/723636/723646 FIFOs can be combined with unidirec-
tionalFIFOscapableofFirstWordFallThroughtiming(i.e.theSuperSyncFIFO
family) to form a depth expansion.
If, at any time, the FIFO is not actively performing a function, the chip
will automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT723626/723636/723646s are characterized for operation from
0
°C to 70°C. Industrial temperature range (–40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT723646L12PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L15PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L15PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723651L15PF | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723651L15PF8 | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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