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参数资料
| 型号： | IDT723646L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/35页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 2048X36 128QFP |
| 标准包装： | 72 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 72K（2K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723646L12PF |
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14
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
FULL/INPUT READY FLAGS (
FFA/IRA, FFC/IRC)
These are dual purpose flags. In FWFT mode, the Input Ready (IRA and
IRC) function is selected. In IDT Standard mode, the Full Flag (
FFAandFFC)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time a
word is written to a FIFO, its write pointer is incremented. The state machine that
controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH transition
on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input
Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing
clock begins the first synchronization cycle of a read if the clock transition
occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent
clock cycle can be the first synchronization cycle (see Figures 20, 21, 22,
and 23).
ALMOST-EMPTY FLAGS (
AEA,AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the contents of register X1 for
AEB and
register X2 for
AEA.TheseregistersareloadedwithpresetvaluesduringaFIFO
reset, programmed from Port A, or programmed serially (see Almost-Empty flag
and Almost-Full flag offset programming section). An Almost-Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its FIFO contains
(X+1) or more words. A data word present in the FIFO output register has been
read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clock are required after a FIFO write for its Almost-Empty flag to reflect the
new level of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1)
or more words remains LOW if two cycles of its synchronizing clock have not
elapsedsincethewritethatfilledthememorytothe(X+1)level.AnAlmost-Empty
flagissetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclock
aftertheFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)
words. Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figures 24 and 25).
ALMOST-FULL FLAGS (
AFA, AFC)
The Almost-Full flag of a FIFO is synchronized to the port clock that
writes data to its array. The state machine that controls an Almost-Full flag
monitors a write pointer and read pointer comparator that indicates when
the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The
almost-full state is defined by the contents of register Y1 for
AFAandregisterY2
for
AFC. These registers are loaded with preset values during a FlFO reset,
programmed from Port A, or programmed serially (see Almost-Empty flag and
Almost-Full flag offset programming section). An Almost-Full flag is LOW when
the number of words in its FIFO is greater than or equal to (256-Y), (512-Y),
or (1,024-Y) for the IDT723626, IDT723636, or IDT723646 respectively. An
Almost-Full flag is HIGH when the number of words in its FIFO is less than or
equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723626,
IDT723636, or IDT723646 respectively. Note that a data word present in the
FIFO output register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)] or
lesswordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethereadthatreducedthenumberofwordsinmemoryto[256/512/1,024-
(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition
ofitssynchronizingclockaftertheFIFOreadthatreducesthenumberofwords
in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-
Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccursat
time tSKEW2 or greater after the read that reduces the number of words in
memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent synchronizing
clock cycle may be the first synchronization cycle (see Figures 26 and 27).
MAILBOX REGISTERS
Each FIFO has an 18-bit bypass register allowing the passage of
command and control information from Port A to Port B or from Port C to Port
A without putting it in queue. The Mailbox Select (MBA, MBB and MBC) inputs
choose between a mail register and a FIFO for a port data transfer operation.
TheusablewidthofboththeMail1andMail2registersmatchestheselectedbus
size for ports B and C.
When sending data from Port A to Port B via the Mail1 Register, the
followingisthecase:ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1
Register when a Port A write is selected by
CSA, W/RA, and ENA with MBA
HIGH.IftheselectedPortBbussizeis18bits,thentheusablewidthoftheMail1
Register employs data lines A0-A17. (In this case, A18-A35 are don’t care
inputs.)IftheselectedPortBbussizeis9bits,thentheusablewidthoftheMail1
RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’tcareinputs.)
WhensendingdatafromPortCtoPortAviatheMail2Register,thefollowing
isthecase:ALOW-to-HIGHtransitiononCLKCwritesdatatotheMail2Register
when a Port C write is selected by WENC with MBC HIGH. If the selected Port
C bus size is 18 bits, then the usable width of the Mail2 Register employs data
lines C0-C17. If the selected Port C bus size is 9 bits, then the usable width of
the Mail2 Register employs data lines C0-C8. (In this case, C9-C17 are don’t
care inputs.)
Writing data to a mail register sets its corresponding flag (
MBF1 or MBF2)
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port mailbox select input is HIGH.
The Mail1 Register Flag (
MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by
CSB, and RENB with MBB HIGH.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. For the
9-bit bus size, 9 bits of mailbox data are placed on B0-B8. (In this case, B9-B17
are indeterminate.)
The Mail2 Register Flag (
MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH.Thedatainamailregisterremainsintactafteritisreadandchangesonly
whennewdataiswrittentotheregister.Foran18-bitbussize,18bitsofmailbox
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相关代理商/技术参数 |
参数描述 |
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| IDT723646L12PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L15PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L15PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723651L15PF | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723651L15PF8 | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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