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参数资料
| 型号： | IDT723673L15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/29页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 8192X36 128QFP |
| 标准包装： | 36 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 288K（8K x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723673L15PF |
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10
COMMERCIALTEMPERATURERANGE
IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofReset,theBEselectfunctionisactive,
permittingachoiceofBig-orLittle-Endianbytearrangementfordatareadfrom
Port B. This selection determines the order by which bytes (or words) of data
are transferred through this port. For the following illustrations, assume that a
byte (or word) bus size has been selected for Port B. (Note that when Port B
is configured for a long word size, the Big-Endian function has no application
and the BE input is a “don’t care”1.)
A HIGH on the BE/
FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaBig-Endianarrangement.Inthiscase,themostsignificant
byte (word) of the long word written to Port A will be read from Port B first; the
least significant byte (word) of the long word written to Port A will be read from
Port B last.
A LOW on the BE/
FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaLittle-Endianarrangement.Inthiscase,theleastsignificant
byte (word) of the long word written to Port A will be read from Port B first; the
most significant byte (word) of the long word written to Port A will be read from
Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure
3 (Reset) for an Endian select timing diagram.
— TIMING MODE SELECTION
AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT) mode. Once the Reset (
RS1)inputisHIGH,aHIGHontheBE/FWFT
inputduringthenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectIDT
Standard mode. This mode uses the Empty Flag function (
EF) to indicate
whether or not there are any words present in the FIFO memory. It uses the
FullFlagfunction(
FF)toindicatewhetherornottheFIFOmemoryhasanyfree
space for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using a formal read operation.
Once the Reset (
RS1) input is HIGH, a LOW on the BE/FWFT inputduring
the next LOW-to-HIGH transition of CLKA and CLKB will select FWFT mode.
ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere
is valid data at the data outputs (B0-B35). It also uses the Input Ready function
(IR) to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Reset, the level applied to the BE/
FWFT input to choose the
desired timing mode must remain static throughout FIFO operation. Refer to
Figure 3 (Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Two registers in the IDT723653/723663/723673 are used to hold the offset
valuesfortheAlmost-EmptyandAlmost-Fullflags.TheAlmost-Emptyflag(
AE)
Offset register is labeled X and Almost-Full flag (
AF)Offsetregisterislabeled
Y. The offset registers can be loaded with preset values during the reset of the
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmed in serial using the Serial Data (SD) input (see Table 1). FS2 FS0/
SD, and FS1/
SEN function the same way in both IDT Standard and FWFT
modes.
SIGNAL DESCRIPTION
RESET (
RS1, RS2)
After power up, a Reset operation must be performed by providing a LOW
pulse to
RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the
IDT723653/723663/723673 undergoes a complete reset by taking its Reset
(
RS1 and RS2) input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A Reset initializes the internal read and write
pointers and forces the Full/Input Ready flag (
FF/IR)LOW,theEmpty/Output
Ready flag (
EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-
Full flag (
AF) HIGH. A Reset (RS1) also forces the Mailbox flag (MBF1) of the
parallelmailboxregisterHIGH,andatthesametimethe
RS2andMBF2operate
likewise. After a Reset, the FIFO’s Full/Input Ready flag is set HIGH after two
write clock cycles to begin normal operation.
A LOW-to-HIGH transition on the FlFO Reset (
RS1)inputlatchesthevalue
of the Big-Endian (BE) input for determining the order by which bytes are
transferred through Port B.
A LOW-to-HIGH transition on the FlFO Reset (
RS1) input also latches the
values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost-
FullandAlmost-Emptyoffsetprogrammingmethod(fordetailsseeTable1,Flag
Programming, and Almost-Empty and Almost-Full flag offset programming
section). The relevant Reset timing diagram can be found in Figure 3.
PARTIAL RESET (
PRS)
The FIFO memory of the IDT723653/723663/723673 undergoes a limited
reset by taking its Partial Reset (
PRS) input LOW for at least four Port A clock
(CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The RTM pin
mustbeLOWduringthetimeofPartialReset.ThePartialResetinputcanswitch
asynchronously to the clocks. A Partial Reset initializes the internal read and
write pointers and forces the Full/Input Ready flag (
FF/IR) LOW, the Empty/
Output Ready flag (
EF/OR) LOW, the Almost-Empty flag (AE) LOW, and the
Almost-Fullflag(
AF)HIGH.APartialResetalsoforcestheMailboxflag(MBF1,
MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,theFIFO’s
Full/Input Ready flag is set HIGH after two Write Clock cycles to begin normal
operation. See Figure 4, Partial Reset (IDT Standard and FWFT Modes) for
the relevant timing diagram.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Reset would be inconvenient.
RETRANSMIT (
RT)
The FIFO memory of these devices undergoes a Retransmit by taking its
associatedRetransmit(
RT)inputLOWforatleastfourPortAClock(CLKA)and
four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit initializes
the read pointer of FIFO to the first memory location.
The RTM pin must be HIGH during the time of Retransmit. Note that the
RT
inputismuxedwiththe
PRSinput,thestateoftheRTMpindeterminingwhether
this pin performs a Retransmit or a Partial Reset. See Figure 19 for Retransmit
(Standard IDT mode) and Figure 20 for Retransmit (FWFT mode) timing
diagrams.
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
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相关代理商/技术参数 |
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| IDT723673L15PF8 | 功能描述:IC FIFO SYNC 8192X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L12PF | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L12PF8 | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L15PF | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L15PF8 | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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