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| 型号： | IDT72T3655L5BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 56/57页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 2048X36 5NS 208-BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，同步 |
| 存储容量： | 72K（2K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 5ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BGA |
| 供应商设备封装： | 208-PBGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72T3655L5BB |
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8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
PRS
PartialReset
HSTL-LVTTL
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q0–Q35 DataOutputs
HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not
OUTPUT
be connected. Outputs are not 5V tolerant regardless of the state of
OE and RCS.
RCLK/
Read Clock/
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by
REN,therisingedgeofRCLK
RD
Read Stobe
INPUT
reads data from the FIFO memory and offsets from the programmable registers. If
LD is LOW, the values
loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read
port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.
REN
should be tied LOW.
RCS
Read Chip Select
HSTL-LVTTL
RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
aMasterResetorPartialResetthe
RCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance
regardless of
RCS.
REN
Read Enable
HSTL-LVTTL If Synchronous operation of the read port has been selected,
REN enablesRCLK for reading data from the
INPUT
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the
REN
input should be tied LOW.
RHSTL
(1) Read Port HSTL
LVTTL
This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select
INPUT
required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT
Retransmit
HSTL-LVTTL
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
INPUT
HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode
or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump
to the ‘mark’ location.
SCLK
Serial Clock
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT
SEN is enabled.
SEN
Serial Enable
HSTL-LVTTL
SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL
System HSTL
LVTTL
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select
INPUT
TCK(2)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
INPUT
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Input
INPUT
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Output
OUTPUT
test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
TMS(2)
JTAG Mode
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
Select
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(2) JTAGReset
HSTL-LVTTL
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
INPUT
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use
TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
WEN
WriteEnable
HSTL-LVTTL When Synchronous operation of the write port has been selected,
WEN enables WCLK for writing data into
INPUT
theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
WCS
WriteChipSelect
HSTL-LVTTL The
WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WCLK/
WriteClock/
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by
WEN,therisingedgeofWCLK
WR
WriteStrobe
INPUT
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (
WEN should be tied to its active state).
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| IDT72T3655L5BBI | 功能描述:IC FIFO 2048X36 5NS 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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| IDT72T3665L4-4BB | 功能描述:IC FIFO 4096X36 4-4NS 208-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T3665L4-4BBG | 功能描述:IC FIFO 4096X36 4-4NS 208-BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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