- 您现在的位置：买卖IC网 > PDF目录10031 > IDT72V3613L15PF8 (IDT, Integrated Device Technology Inc)IC FIFO CLOCK 64X36 15NS 120TQFP PDF资料下载
参数资料
| 型号： | IDT72V3613L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 19/25页 |
| 文件大小： | 0K |
| 描述： | IC FIFO CLOCK 64X36 15NS 120TQFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 2.3K（64 x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V3613L15PF8 |
3
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AE
Almost-EmptyFlag
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when Port B the number of 36-bit
Port B words in the FIFO is less than or equal to the value in the offset register, X.
AF
Almost-FullFlag
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty
Port A empty locations in the FIFO is less than or equal to the value in the offset register, X.
B0-B35
Port B Data
I/O
36-bit bidirectional data port for side B
BE
Big-EndianSelect
I
Selects the bytes on port B used during byte or word FIFO reads. A LOW on BE selects the most
significant bytes on B0-B35 for use, and a HIGH selects theleastsignificantbytes.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB. EF and AE are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip Select
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-
A35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-
B35 outputs are in the high-impedance state when CSB is HIGH.
EF
Empty Flag
O
EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty, and
Port B reads from its memory are disabled. Data can be read from the FIFO to its output register when EF is
HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after data is loaded into empty FIFO memory.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FF
Full Flag
O
FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and
Port A writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the
secondLOW-to-HIGHtransitionofCLKAafterreset.
FS1, FS0 FlagOffsetSelects
I
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four preset
valuesintotheAlmost-FullflagandAlmost-Emptyflagoffsets.
MBA
Port A Mailbox
I
A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
Select
outputs are active, mail2 register data is output.
MBF1
Mail1 Register Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the
device is reset.
MBF2
Mail2 Register Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of
CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
ODD/
Odd/Even Parity
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
EVEN
Select
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
PEFA
Port A Parity Error
O
When any valid byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes (PortA)are organized
Flag
as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input.
The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flag is forced HIGH
regardless of the state of the A0-A35 inputs.
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2174CUKG-14#TRPBF | IC ADC 14BIT 105MSPS QUAD 52QFN |
| LTC2153IUJ-14#TRPBF | IC ADC 14BIT DUAL 310MSPS 40QFN |
| MS3112E24-61PX | CONN RCPT 61POS BOX MNT W/PINS |
| AD679AJ | IC ADC 14BIT SAMPLING 44-JLCC |
| VI-26M-MX-F3 | CONVERTER MOD DC/DC 10V 75W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3613L15PQF | 功能描述:IC FIFO CLOCK 64X36 15NS 132PQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3613L20PF | 功能描述:IC FIFO CLOCK 64X36 20NS 120TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3613L20PF8 | 功能描述:IC FIFO CLOCK 64X36 20NS 120TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3613L20PQF | 功能描述:IC FIFO CLOCK 64X36 20NS 132PQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3614L12PF | 功能描述:IC FIFO 64X36X2 12NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
发布紧急采购，3分钟左右您将得到回复。