参数资料
型号: IDT72V3614L20PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 19/32页
文件大小: 0K
描述: IC FIFO 64X36X2 20NS 120QFP
标准包装: 45
系列: 72V
功能: 异步,同步
存储容量: 4.6K(64 x 36 x2)
数据速率: 50MHz
访问时间: 20ns
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 120-LQFP
供应商设备封装: 120-TQFP(14x14)
包装: 托盘
其它名称: 72V3614L20PF
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
26
Figure 17. FFB
FFB
FFB Flag Timing and First Available Write when FIFO2 is Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, either SIZ1 = LOW or SIZ0 = LOW).
3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AEB is set LOW by the last word or byte read of the long word,
respectively.
Figure 18. Timing for AEB
AEB
AEB when FIFO1 is Almost-Empty
CSA
EFA
MBA
ENA
A0 - A35
CLKA
FFB
CLKB
CSB
4663 drw 17
W
RB
12
B0 - B35
SIZ1,
SIZ0
ENB
tCLK
tCLKH
tCLKL
tENS
tENH
tA
tSKEW1
tCLK
tCLKH
tCLKL
tENS
tDS
tENH
tDH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/
RA
LOW
HIGH
LOW
HIGH
(1)
FIFO2 Full
tWFF
AEB
CLKA
ENB
4663 drw 18
ENA
CLKB
2
1
tENS
tENH
tSKEW2
tPAE
tENS
tENH
X Long Word in FIFO1
(X+1) Long Words in FIFO1
(1)
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, FFB is set LOW by the last word or byte write of the long word,
respectively.
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