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参数资料
| 型号： | IDT72V3614L20PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 23/32页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 64X36X2 20NS 120QFP |
| 标准包装： | 45 |
| 系列： | 72V |
| 功能： | 异步，同步 |
| 存储容量： | 4.6K（64 x 36 x2） |
| 数据速率： | 50MHz |
| 访问时间： | 20ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 72V3614L20PF |
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IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
3
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AEA
PortAAlmost-
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of 36-bit words in
Empty Flag
(Port A) FIFO2 is less than or equal to the value in the offset register, X.
AEB
PortBAlmost-
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of 36-bit words in
Empty Flag
(Port B) FIFO1 is less than or equal to the value in the offset register, X.
AFA
PortAAlmost-Full
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty
Flag
(Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
AFB
PortBAlmost-Full
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of 36-bit empty
Flag
(Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
B0-B35
Port B Data
I/O
36-bit bidirectional data port for side B.
BE
Big-EndianSelect
I
Selects the bytes on port B used during byte or word data transfer. A LOW on BE selects the most significant
bytes on B0-B35 for use, and a HIGH selects the least significant bytes.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or
coincident to CLKA. Port B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip Select
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EFA
Port A Empty Flag
O
EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA isLOW, FIFO2 is empty, and
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is
HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.
EFB
Port B Empty Flag
O
EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is empty, and
(Port B) and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is
HIGH. EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after data is loaded into empty FIFO1 memory.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA
Port A Full Flag
O
FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA
is LOW, FIFO1 is full, and writes
(Port A) to its memory are disabled. FFA is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGHtransitionofCLKAafterreset.
FFB
Port B Full Flag
O
FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full, and writes
(Port B) writes to its memory are disabled. FFB is forced LOW when the device is reset and is set HIGH by the
secondLOW-to-HIGHtransitionofCLKBafterreset.
FS1, FS0 Flag-Offset
I
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four preset
Selects
valuesfortheAlmost-FullflagandAlmost-Emptyflagoffset.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
Select
outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level
selects FIFO2 output register data for output.
MBF1
Mail1Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
Flag
mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the
device is reset.
PIN DESCRIPTION
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| IDT72V3614L20PF8 | 功能描述:IC FIFO 64X36X2 20NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3614L20PQF | 功能描述:IC FIFO 64X36X2 20NS 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3622L10PF | 功能描述:IC BIFIFO 256X36X2 10NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3622L10PF8 | 功能描述:IC BIFIFO 256X36X2 10NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3622L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC BIFIFO 256X36X2 10NS 120-TQFP |
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