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| 型号： | IDT72V3614L20PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/32页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 64X36X2 20NS 120QFP |
| 标准包装： | 45 |
| 系列： | 72V |
| 功能： | 异步，同步 |
| 存储容量： | 4.6K（64 x 36 x2） |
| 数据速率： | 50MHz |
| 访问时间： | 20ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 72V3614L20PF |
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IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
11
ThelevelsappliedtotheportBbusSizeselect(SIZ0,SIZ1)inputsandthe
Big-Endianselect(BE)inputarestoredoneachCLKBLOW-to-HIGHtransition.
ThestoredportBbussizeselectionisimplementedbythenextrisingedgeon
CLKB according to Figure 2.
Only36-bitlong-worddataiswrittentoorreadfromthetwoFIFOmemories
ontheIDT72V3614.Bus-matchingoperationsaredoneafterdataisreadfrom
theFIFO1RAMandbeforedataiswrittentotheFIFO2RAM.PortBbussizing
does not apply to mail register operations.
BUS-MATCHING FIFO1 READS
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.Ifalong
word bus size is implemented, the entire long word immediately shifts to the
FIFO1 output register. If byte or word size is implemented on port B, only the
firstoneortwobytesappearontheselectedportionoftheFIFO1outputregister,
withtherestofthelongwordstoredinauxiliaryregisters.Inthiscase,subsequent
FIFO1readswiththesamebus-sizeimplementationoutputtherestofthelong
word to the FIFO1 output register in the order shown by Figure 2.
EachFIFO1readwithanewbus-sizeimplementationautomaticallyunloads
datafromtheFIFO1RAMtoitsoutputregisterandauxiliaryregisters.Therefore,
implementinganewportBbussizeandperformingaFIFO1readbeforeallbytes
orwordsstoredintheauxiliaryregistershavebeenreadresultsinalossofthe
unread long word data.
WhenreadingdatafromFIFO1inbyteorwordformat,theunusedB0-B35
outputsareindeterminate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. FIFO2
writes,withalong-wordbussize,immediatelystoreeachlongwordinFIFO2
RAM.DatawrittentoFIFO2withabyteorwordbussizestorestheinitialbytes
orwordsinauxiliaryregisters.TheCLKBrisingedgethatwritesthefourthbyte
or the second word of long word to FIFO2 also stores the entire long word in
FIFO2 RAM. The bytes are arranged in the manner shown in Figure 2.
Each FIFO2 write with a new bus-size implementation resets the state
machinethatcontrolsthedataflowfromtheauxiliaryregisterstotheFIFO2RAM.
Therefore,implementinganewbussizeandperformingaFIFO2writebefore
bytesorwordsstoredintheauxiliaryregistershavebeenloadedtoFIFO2RAM
results in a loss of data.
WhenwritingdatatoFIFO2inbyteorwordformat,theunusedB0-B35inputs
are don't care(1) inputs.
PORT-B MAIL REGISTER ACCESS
Inadditiontoselectingport-BbussizesforFIFOreadsandwrites,theport
BbusSizeselect(SIZ0,SIZ1)inputsalsoaccessthemailregisters.Whenboth
SIZ0andSIZ1areHIGH,themail1registerisaccessedforaportBlongword
read and the mail2 register is accessed for a port B long word write. The mail
register is accessed immediately and any bus-sizing operation that may be
underwayisunaffectedbythemailregisteraccess.Afterthemailregisteraccess
iscomplete,thepreviousFIFOaccesscanresumeinthenextCLKBcycle.The
logicdiagraminFigure3showsthepreviousbus-sizeselectionispreserved
when the mail registers are accessed from port B. A port B bus size is
implemented on each rising CLKB edge according to the states of SIZ0_Q,
SIZ1_Q, and BE_Q.
BYTE SWAPPING
The byte-order arrangement of data read from FIFO1 or data written to
FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order
swapping is not available for mail register data. Four modes of byte-order
swapping (including no swap) can be done with any data port size selection.
cycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)
longwords. Otherwise,thesubsequentsynchronizingclockcyclecanbethe
first synchronization cycle (see Figure 18 and 19).
ALMOST FULL FLAGS (AFA, AFB)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray. ThestatemachinethatcontrolsanAlmost-Fullflagmonitors
a write-pointer and read-pointer comparator that indicates when the FIFO
memorystatusisalmostfull,almostfull-1,oralmostfull-2. Thealmost-fullstate
isdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X).
Thisregisterisloadedwithoneoffourpresetvaluesduringadevicereset(see
Resetsection). AnAlmost-FullflagisLOWwhentheFIFOcontains(64-X)or
more long words in memory and is HIGH when the FIFO contains [64-(X+1)]
or less long words.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
requiredafteraFIFOreadfortheAlmost-Fullflagtoreflectthenewleveloffill.
Therefore,theAlmost-FullflagofaFIFOcontaining[64-(X+1)]orlesswords
remainsLOWiftwocyclesofthesynchronizingclockhavenotelapsedsince
the read that reduced the number of long words in memory to [64-(X+1)]. An
Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of the
synchronizingclockaftertheFIFOreadthatreducesthenumberoflongwords
in memory to [64-(X+1)]. A LOW-to-HIGH transition of an Almost-Full flag
synchronizing clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of long words in
memoryto[64-(X+1)]. Otherwise,thesubsequentsynchronizingclockcycle
can be the first synchronization cycle (see Figure 20 and 21).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
informationbetweenportAandportBwithoutputtingitinqueue. TheMailbox
Select (MBA, SIZ0, SIZ1) inputs choose between a mail register and a FIFO
foraportdatatransferoperation. ALOW-to-HIGHtransitiononCLKAwrites
A0-A35 data to the mail1 register when a port A write is selected by CSA, W/
RA,andENAwithMBAHIGH. ALOW-to-HIGHtransitiononCLKBwritesB0-
B35 data to the mail2 register when a port B write is selected by CSB, W/RB,
and ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail register sets
thecorrespondingflag(MBF1orMBF2)LOW. Attemptedwritestoamailregister
are ignored while the mail flag is LOW.
WhentheportAdataoutputs(A0-A35)areactive,thedataonthebuscomes
fromtheFIFO2outputregisterwhenMBAisLOWandfromthemail2register
whenMBAisHIGH.WhentheportBdataoutputs(B0-B35)areactive,thedata
onthebuscomesfromtheFIFO1outputregisterwheneitheroneorbothSIZ1
and SIZ0 are LOW and from the mail2 register when both SIZ1 and SIZ0 are
HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a rising CLKB edge
when a port B read is selected by CSB, W/RB, and ENB with both SIZ1 and
SIZ0 HIGH. The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH
transitiononCLKAwhenportAreadisselectedbyCSA,W/RA,andENAand
MBA is HIGH. The data in the mail register remains intact after it is read and
changes only when new data is written to the register. Relevant mail register
andMailRegisterFlagtimingdiagramscanbefoundinFigure22andFigure23.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-
bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-
sizebusselectionscanutilizethemostsignificantbytesofthebus(Big-Endian)
orleastsignificantbytesofthebus(Little-Endian).PortBbussizecanbechanged
dynamically and synchronous to CLKB to communicate with peripherals of
various bus widths.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3614L20PF8 | 功能描述:IC FIFO 64X36X2 20NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3614L20PQF | 功能描述:IC FIFO 64X36X2 20NS 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3622L10PF | 功能描述:IC BIFIFO 256X36X2 10NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3622L10PF8 | 功能描述:IC BIFIFO 256X36X2 10NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3622L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC BIFIFO 256X36X2 10NS 120-TQFP |
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