参数资料
型号: IDT72V3680L10PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 35/46页
文件大小: 0K
描述: IC FIFO SS 16384X36 10NS 128TQFP
标准包装: 1,000
系列: 72V
功能: 异步,同步
存储容量: 576K(16K x 36)
数据速率: 100MHz
访问时间: 10ns
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 带卷 (TR)
其它名称: 72V3680L10PF8
40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the
EFand FFfunctionsinIDTStandardmodeandtheIR
and
ORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
and WCLK, it is possible for
EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
Figure 29. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72 and 32,768 x 72 Width Expansion
avoided by creating composite flags, that is, ANDing
EF of every FIFO, and
separately ANDing
FFofeveryFIFO. InFWFTmode,compositeflagscanbe
created by ORing
OR ofeveryFIFO,andseparatelyORing IRof every FIFO.
Figure 29 demonstrates a width expansion using two IDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690devices. D0 - D35 from each
device form a 72-bit wide input bus and Q0-Q35 from each device form a 72-
bit wide output bus. Any word width can be attained by adding additional
IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 devices.
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
4667 drw34
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
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