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参数资料
| 型号： | IDT72V51246L7-5BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 54/56页 |
| 文件大小： | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 标准包装： | 1 |
| 类型： | 多队列流量控制 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72V51246L7-5BB |
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7
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
BM
BusMatching
LVTTL
This pin is setup before Master Reset and must not toggle during any device operation. This pin is used
INPUT
along with IW and OW to setup the multi-queue flow-control device bus width. Please refer to Table 3
fordetails.
D[35:0]
Data Input Bus
LVTTL
These are the 36 data input pins. Data is written into the device via these input pins on the rising edge
Din
INPUT
of WCLK provided that
WEN is LOW. Note, that in Packet mode D32-D35 may be used as packet
markers,pleaseseepacketreadyfunctionaldiscussionformoredetail.Duetobusmatchingnotallinputs
may be used, any unused inputs should be tied LOW.
DF(1)
Default Flag
LVTTL
If the user requires default programming of the multi-queue device, this pin must be setup before Master
INPUT
Reset and must not toggle during any device operation. The state of this input at master reset determines
the value of the
PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
DFM(1)
Default Mode
LVTTL
The multi-queue device requires programming after master reset. The user can do this serially via the
INPUT
serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be
selected, if HIGH then default mode is selected.
ESTR
PAEn Flag Bus
LVTTL
If direct operation of the
PAEn bus has been selected, the ESTR input is used in conjunction with RCLK
Strobe
INPUT
and the RDADD bus to select a device for its queues to be placed on to the
PAEn bus outputs. A device
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a
PAEn flag bus
selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
and
SENO has gone LOW.
ESYNC
PAEn Bus Sync
LVTTL
ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the
PAEn bus
OUTPUT
during Polled operation of the
PAEn bus. During Polled operation each devices queue status flags are
loadedontothe
PAEnbusoutputssequentiallybasedonRCLK.ThefirstRCLKrisingedgeloadsdevice1
on to
PAEn,thesecondRCLKrisingedgeloadsdevice2andsoon.DuringtheRCLKcyclethataselected
device is placed on to the
PAEn bus, the ESYNC output will be HIGH.
EXI
PAEn/PRnBus
LVTTL
The EXI input is used when multi-queue devices are connected in expansion mode and Polled
PAEn/
Expansion In
INPUT
PRn bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The
EXI receives a token from the previous device in a chain. In single device mode the EXI input must be
tied LOW if the
PAEn/PRnbusisoperatedindirectmode.IfthePAEn/PRnbusisoperatedinpolledmode
the EXI input must be connected to the EXO output of the same device. In expansion mode the EXI of
the first device should be tied LOW, when direct mode is selected.
EXO
PAEn/PRnBus
LVTTL
EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
Expansion Out
OUTPUT
PAEn/PRnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.
This pin pulses HIGH when device N places its
PAEstatusontothePAEn/PRnbuswithrespecttoRCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edge the first quadrant of device N+1 will be loaded on to the
PAEn/PRnbus.Thiscontinuesthroughthe
chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each
device in the chain provides synchronization to the user of this looping event.
FF
Full Flag
LVTTL
This pin provides the full flag output for the active queue, that is, the queue selected on the input port
OUTPUT
for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue
selection, this flag will show the status of the newly selected queue. Data can be written to this queue on
the next cycle provided
FF is HIGH. This flag has High-Impedance capability, this is important during
expansionofdevices,whenthe
FFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line. The device with a queue selected takes control of the
FFbus,allotherdevicesplacetheirFFoutput
into High-Impedance. When a queue selection is made on the write port this output will switch from
High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.
FM(1)
Flag Mode
LVTTL
This pin is setup before a master reset and must not toggle during any device operation. The state of the
INPUT
FM pin during Master Reset will determine whether the
PAFn and PAEn flag busses operate in either
Polled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
FSTR
PAFn Flag Bus
LVTTL
If direct operation of the
PAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
Strobe
INPUT
and the WRADD bus to select a device for its queues to be placed on to the
PAFn bus outputs. A device
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
PIN DESCRIPTIONS
Symbol
Name
I/O TYPE
Description
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| IDT72V51246L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51246L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BBG | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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