- 您现在的位置：买卖IC网 > PDF目录4584 > IDT72V51246L7-5BB (IDT, Integrated Device Technology Inc)IC FLOW CTRL MULTI QUEUE 256-BGA PDF资料下载
参数资料
| 型号： | IDT72V51246L7-5BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/56页 |
| 文件大小： | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 标准包装： | 1 |
| 类型： | 多队列流量控制 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72V51246L7-5BB |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页
17
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
FUNCTIONAL DESCRIPTION
MASTER RESET
A Master Reset is performed by toggling the
MRSinputfromHIGHtoLOW
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol
registers are initialized and require programming either serially by the user via
the serial port, or using the default settings. During a master reset the state of
thefollowinginputsdeterminethefunctionalityofthepart,thesepinsshouldbe
held HIGH or LOW.
PKT – Packet Mode
FM – Flag bus Mode
IW, OW, BM – Bus Matching options
MAST – Master Device
ID0, 1, 2 – Device ID
DFM – Programming mode, serial or default
DF – Offset value for
PAE and PAF
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither
serially or via the default method before any read/write operations can begin.
See Figure 4, Master Reset for relevant timing.
PARTIAL RESET
APartialResetisameansbywhichtheusercanresetboththereadandwrite
pointers of a single queue that has been setup within a multi-queue device.
Before a partial reset can take place on a queue, the respective queue must be
selectedonboththereadportandwriteportaminimumof2RCLKand2WCLK
cyclesbeforethe
PRSgoesLOW.Thepartialresetisthenperformedbytoggling
the
PRSinputfromHIGHtoLOWtoHIGH,maintainingtheLOWstateforatleast
oneWCLKandoneRCLKcycle.Onceapartialresethastakenplaceaminimum
of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can
occur.
A Partial Reset only resets the read and write pointers of a given queue, a
partialresetwillnoteffecttheoverallconfigurationandsetupofthemulti-queue
device and its queues.
See Figure 5, Partial Reset for relevant timing.
SERIAL PROGRAMMING
The multi-queue flow-control device is a fully programmable device, provid-
ing the user with flexibility in how queues are configured in terms of the number
of queues, depth of each queue and position of the
PAF/PAE flags within
respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster
reset has taken place. Internally the multi-queue device has setup registers
which must be serially loaded, these registers contain values for every queue
within the device, such as the depth and
PAE/PAF offset values. The
IDT72V51236/72V51246/72V51256 devices are capable of up to 4 queues
and therefore contain 4 sets of registers for the setup of each queue.
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice
will require serial programming by the user. It is recommended that the user
utilize a ‘C’ program provided by IDT, this program will prompt the user for all
information regarding the multi-queue setup. The program will then generate
a serial bit stream which should be serially loaded into the device via the serial
port. For the IDT72V51236/72V51246/72V51256 devices the serial program-
ming requires a total number of serially loaded bits per device, (SCLK cycles
with
SENIenabled),calculatedby:19+(Qx72)whereQisthenumberofqueues
the user wishes to setup within the device. Please refer to the separate
Application Note, AN-303 for recommended control of the serial programming
port.
Once the master reset is complete and
MRS is HIGH, the device can be
serially loaded. Data present on the SI (serial in), input is loaded into the serial
port on a rising edge of SCLK (serial clock), provided that
SENI (serial in
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully
completedthedevicewillindicatethisviathe
SENO(serialoutputenable)going
active, LOW. Upon detection of completion of programming, the user should
ceaseallprogrammingandtake
SENIinactive,HIGH.Note,SENOfollowsSENI
onceprogrammingofadeviceiscomplete.Therefore,
SENOwillgoLOWafter
programming provided
SENIisLOW,onceSENIistakenHIGHagain,SENO
willalsogoHIGH.TheoperationoftheSOoutputissimilar,whenprogramming
of a given device is complete, the SO output will follow the SI input.
Ifdevicesarebeingusedinexpansionmodetheserialportsofdevicesshould
becascaded.Theusercanloadalldevicesviatheserialinputportcontrolpins,
SI &
SENI, of the first device in the chain. Again, the user may utilize the ‘C’
program to generate the serial bit stream, the program prompting the user for
the number of devices to be programmed. The
SENO and SO (serial out) of
the first device should be connected to the
SENI and SI inputs of the second
device respectively and so on, with the
SENO&SOoutputsconnectingtothe
SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould
be monitored by the user. When
SENO of the final device goes LOW, this
indicates that serial programming of all devices has been successfully com-
pleted.Upondetectionofcompletionofprogramming,theusershouldceaseall
programming and take
SENI of the first device in the chain inactive, HIGH.
As mentioned, the first device in the chain has its serial input port controlled
by the user, this is the first device to have its internal registers serially loaded
bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake
its
SENO output LOW and bypass the serial data loaded on the SI input to its
SO output. The serial input of the second device in the chain is now loaded with
the data from the SO of the first device, while the second device has its
SENI
input LOW. This process continues through the chain until all devices are
programmed and the
SENO of the final device goes LOW.
Once all serial programming has been successfully completed, normal
operations, (queue selections on the read and write ports) may begin. When
connected in expansion mode, the IDT72V51236/72V51246/72V51256 de-
vices require a total number of serially loaded bits per device to complete serial
programming, (SCLK cycles with
SENIenabled),calculatedby:n[19+(Qx72)]
where Q is the number of queues the user wishes to setup within the device,
where n is the number of devices in the chain.
See Figure 6, Serial Port Connection and Figure 7, Serial Programming for
connectionandtiminginformation.
DEFAULT PROGRAMMING
During a Master Reset if the DFM (Default Mode) input is HIGH the multi-
queue device will be configured for default programming, (serial programming
is not permitted). Default programming provides the user with a simpler,
however limited means by which to setup the multi-queue flow-control device,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possiblearesetup,withallofthepartsavailablememoryblocksbeingallocated
equallybetweenthequeues.Thevaluesofthe
PAE/PAFoffsetsisdetermined
by the state of the DF (default) pin during a master reset.
For the IDT72V51236/72V51246/72V51256 devices the default mode will
setup 4 queues, each queue being 4,096 x 36, 8,192 x 36 and 16,384 x 36
deep respectively. For both devices the value of the
PAE/PAF offsets is
determined at master reset by the state of the DF input. If DF is LOW then both
the
PAE & PAF offset will be 8, if HIGH then the value is 128.
When configuring the IDT72V51236/72V51246/72V51256 devices in de-
fault mode the user simply has to apply WCLK cycles after a master reset, until
SENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.Theseclock
相关PDF资料 |
PDF描述 |
|---|---|
| MIC5322-PNYMT TR | IC REG LDO 3V/2.85V .15A 6MLF |
| IDT72V51446L7-5BB8 | IC FLOW CTRL MULTI QUEUE 256-BGA |
| LFECP10E-3FN484I | IC FPGA 10.2KLUTS 484FPBGA |
| LFECP10E-4FN484C | IC FPGA 10.2KLUTS 484FPBGA |
| LFEC10E-3FN484I | IC FPGA 10.2KLUTS 484FPBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V51246L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51246L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BBG | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
发布紧急采购，3分钟左右您将得到回复。