- 您现在的位置：买卖IC网 > PDF目录2077 > IDT72V73273BBG (IDT, Integrated Device Technology Inc)IC DGTL SW 32768X32768 208-BGA PDF资料下载
参数资料
| 型号： | IDT72V73273BBG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 33/36页 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 32768X32768 208-BGA |
| 标准包装： | 12 |
| 系列： | 72V |
| 类型： | 多路复用器 |
| 电路： | 8 x 1:1 |
| 电压电源： | 单电源 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BGA |
| 供应商设备封装： | 208-PBGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72V73273BBG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页
6
INDUSTRIAL TEMPERATURERANGE
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
MICROPROCESSOR INTERFACE
The IDT72V73273’s microprocessor interface looks like a standard RAM
interfacetoimproveintegrationintoasystem. Witha16-bitaddressbusand
a16-bitdatabusallmemoriescanbeaccessed. UsingtheTSImicroprocessor
interface,readsandwritesaremappedintoDataandConnectionmemories.
By allowing the internal memories to be randomly accessed, the controlling
microprocessorhasmoretimetomanageotherperipheraldevices
andcanmoreeasilyandquicklygatherinformationandsetuptheswitchpaths.
Table1showsthemappingoftheaddressesintointernalmemoryblocks. In
ordertominimizetheamountofmemorymappedspacehowever,theMemory
Select(MS1-0)bitsintheControlRegistermustbewrittentofirsttoselectbetween
theConnectionMemoryHIGH,theConnectionMemoryLOW,orDataMemory.
Effectively,theMemorySelectbitsactasaninternalmuxtoselectbetweenthe
Data Memory, Connection Memory HIGH, and Connection Memory LOW.
MEMORYMAPPING
Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters
and memoriesoftheIDT72V73273.Themostsignificantbitoftheaddressselect
between the registers and internal memories. See Table 1 for mappings.
Asexplainedintheinitializationsections,aftersystempower-up,theTDRSR
and RDRSR, should be programmed immediately to establish the desired
switchingconfiguration.
The data in the Control Register consists of the Software Reset, RX/TX
Bypass,OutputEnablePolarity,AllOutputEnable,FullBlockProgramming,
BlockProgrammingData,BeginBlockProgrammingEnable,ResetConnection
MemoryLOWinBlockProgramming,OutputStandby,andMemorySelect.
SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As
withthehardreset,theSoftwareResetmustalsobesetHIGHfor20nsbefore
bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware
Reset is LOW, internal registers and other memories may be read or written.
During Software Reset, the microprocessor port is still able to read from all
internalmemories.TheonlywriteoperationallowedduringaSoftwareReset
istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset.
CONNECTION MEMORY CONTROL
If the ODE pin and the Output Standby bit are LOW, all output channels will
be in three-state. See Table 2 for detail.
IfMOD2-0oftheConnectionMemoryHIGHis1-0-0accordingly,theoutput
channel will be in Processor Mode. In this case the lower eight bits of the
Connection Memory LOW are output each frame until the MOD2-0 bits are
changed.IfMOD2-0oftheConnectionMemoryHIGHare0-0-1accordingly,
thechannelwillbeinConstantDelayModeandbits14-0areusedtoaddress
a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are
0-0-0, the channel will be in Variable Delay Mode and bits 14-0 are used to
addressalocationinDataMemory.IfMOD2-0oftheConnectionMemoryHIGH
are 1-1-1, the channel will be in High-Impedance mode and that channel will
beinthree-state.
RX/TX INTERNAL BYPASS
WhentheBypassbitofcontrolregistersis1,allRXstreamswillbe“shorted”
toTX ineffectbypassingallinternalcircuitryoftheTSI. Thiseffectivelysetsthe
TSItoa1-to-1switchmodewithminimalI/Odelay. Azerocanbewrittentoallow
normaloperation.TheintentionofthismodeistominimizethedelayfromtheRX
input to the TX output making the TSI “invisible”.
INITIALIZATION OF THE IDT72V73273
Afterpowerup,thestateoftheConnectionMemoryisunknown. Assuch,the
outputsshouldbeputinHigh-ImpedancebyholdingtheODEpinLOW. While
theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock
Programmingfeatureandprogramtheactivepathsviathemicroprocessorbus.
Oncethedeviceisconfigured,theODEpin(orOutputStandbybitdepending
oninitialization)canbeswitchedtoenabletheTSIswitch.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT72V845L10PF | IC FIFO SYNC 4096X18 128QFP |
| IDT72V851L10TFG | IC FIFO 8192X9 DUAL SYNC 64TQFP |
| IDT72V85L15PAG | IC FIFO ASYNCH 4096X18 56TSSOP |
| IDT72V8980PVG | IC DGTL SW 256X256 48-SSOP |
| IDT72V8981JG | IC DGTL SW 128X128 44-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V801L10PF | 功能描述:IC SYNC FIFO 256X9 10NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V801L10PF8 | 功能描述:IC SYNC FIFO 256X9 10NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V801L10PFG | 功能描述:IC FIFO 256X9 SYNC DUAL 64TQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V801L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 256X9 10NS 64QFP |
| IDT72V801L10TF | 功能描述:IC SYNC FIFO 256X9 10NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
发布紧急采购，3分钟左右您将得到回复。